SCU

Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x4001_FFFF)
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBH : Set USBH to Non-secure State Write 1 to set USBH to non-secure state.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

USBH is a secure module (default)

#1 : 1

USBH is a non-secure module

End of enumeration elements list.

SDH0 : Set SDH0 to Non-secure State Write 1 to set SDH0 to non-secure state.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SDH0 is a secure module (default)

#1 : 1

SDH0 is a non-secure module

End of enumeration elements list.

EBI : Set EBI to Non-secure State Write 1 to set EBI to non-secure state.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

EBI is a secure module (default)

#1 : 1

EBI is a non-secure module

End of enumeration elements list.

PDMA1 : Set PDMA1 to Non-secure State Write 1 to set PDMA1 to non-secure state.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA1 is a secure module (default)

#1 : 1

PDMA1 is a non-secure module

End of enumeration elements list.

SCU_PNSSET4 (PNSSET4)

Peripheral Non-secure Attribution Set Register4 (0x4008_0000~0x4009_FFFF)
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0 : Set I2C0 to Non-secure State Write 1 to set I2C0 to non-secure state.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 is a secure module (default)

#1 : 1

I2C0 is a non-secure module

End of enumeration elements list.

I2C1 : Set I2C1 to Non-secure State Write 1 to set I2C1 to non-secure state.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 is a secure module (default)

#1 : 1

I2C1 is a non-secure module

End of enumeration elements list.

I2C2 : Set I2C2 to Non-secure State Write 1 to set I2C2 to non-secure state.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C2 is a secure module (default)

#1 : 1

I2C2 is a non-secure module

End of enumeration elements list.

SC0 : Set SC0 to Non-secure State Write 1 to set SC0 to non-secure state.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC0 is a secure module (default)

#1 : 1

SC0 is a non-secure module

End of enumeration elements list.

SC1 : Set SC1 to Non-secure State Write 1 to set SC1 to non-secure state.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC1 is a secure module (default)

#1 : 1

SC1 is a non-secure module

End of enumeration elements list.

SC2 : Set SC2 to Non-secure State Write 1 to set SC2 to non-secure state.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC2 is a secure module (default)

#1 : 1

SC2 is a non-secure module

End of enumeration elements list.

SCU_PNPSET0 (PNPSET0)

Peripheral Non-privileged Attribution Set Register0 (0x4000_0000~0x4001_FFFF)
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS : Set SYS to Non-privileged State
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

SYS is a privileged module (default)

#1 : 1

SYS is a non-privileged module

End of enumeration elements list.

PDMA0 : Set PDMA0 to Non-privileged State
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA0 is a privileged module (default)

#1 : 1

PDMA0 is a non-privileged module

End of enumeration elements list.

USBH : Set USBH to Non-privileged State
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

USBH is a privileged module (default)

#1 : 1

USBH is a non-privileged module

End of enumeration elements list.

FMC : Set FMC to Non-privileged State
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

FMC is a privileged module (default)

#1 : 1

FMC is a non-privileged module

End of enumeration elements list.

SDH0 : Set SDH0 to Non-privileged State
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SDH0 is a privileged module (default)

#1 : 1

SDH0 is a non-privileged module

End of enumeration elements list.

EBI : Set EBI to Non-privileged State
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

EBI is a privileged module (default)

#1 : 1

EBI is a non-privileged module

End of enumeration elements list.

PDMA1 : Set PDMA1 to Non-privileged State
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA1 is a privileged module (default)

#1 : 1

PDMA1 is a non-privileged module

End of enumeration elements list.

SCU_PNPSET1 (PNPSET1)

Peripheral Non-privileged Attribution Set Register1 (0x4002_0000~0x4003_FFFF)
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU : Set SCU to Non-privileged State
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

SCU is a privileged module (default)

#1 : 1

SCU is a non-privileged module

End of enumeration elements list.

CRC : Set CRC to Non-privileged State
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRC is a privileged module (default)

#1 : 1

CRC is a non-privileged module

End of enumeration elements list.

CRPT : Set CRPT to Non-privileged State
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRPT is a privileged module (default)

#1 : 1

CRPT is a non-privileged module

End of enumeration elements list.

KS : Set KS to Non-privileged State
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

KS is a privileged module (default)

#1 : 1

KS is a non-privileged module

End of enumeration elements list.

SCU_PNPSET2 (PNPSET2)

Peripheral Non-privileged Attribution Set Register2 (0x4004_0000~0x4005_FFFF)
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDT : Set WDT to Non-privileged State
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDT is a privileged module (default)

#1 : 1

WDT is a non-privileged module

End of enumeration elements list.

RTC : Set RTC to Non-privileged State
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC is a privileged module (default)

#1 : 1

RTC is a non-privileged module

End of enumeration elements list.

EWDT : Set EWDT to Non-privileged State
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

EWDT is a privileged module (default)

#1 : 1

EWDT is a non-privileged module

End of enumeration elements list.

EADC : Set EADC to Non-privileged State
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

EADC is a privileged module (default)

#1 : 1

EADC is a non-privileged module

End of enumeration elements list.

ACMP01 : Set ACMP01 to Non-privileged State
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

ACMP0, ACMP1 are privileged modules (default)

#1 : 1

ACMP0, ACMP1 are non-privileged modules

End of enumeration elements list.

DAC : Set DAC to Non-privileged State
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC is a privileged module (default)

#1 : 1

DAC is a non-privileged module

End of enumeration elements list.

I2S0 : Set I2S0 to Non-privileged State
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2S0 is a privileged module (default)

#1 : 1

I2S0 is a non-privileged module

End of enumeration elements list.

OTG : Set OTG to Non-privileged State
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

OTG is a privileged module (default)

#1 : 1

OTG is a non-privileged module

End of enumeration elements list.

TMR01 : Set TMR01 to Non-privileged State
bits : 14 - 16 (3 bit)
access : read-write

Enumeration:

0 : 0

TMR01 is a privileged module (default)

1 : 1

TMR01 is a non-privileged module

End of enumeration elements list.

TMR23 : Set TMR23 to Non-privileged State
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

TMR23 is a privileged module (default)

#1 : 1

TMR23 is a non-privileged module

End of enumeration elements list.

TMR45 : Set TMR45 to Non-privileged State
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

TMR45 is a privileged module (default)

#1 : 1

TMR45 is a non-privileged module

End of enumeration elements list.

EPWM0 : Set EPWM0 to Non-privileged State
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

EPWM0 is a privileged module (default)

#1 : 1

EPWM0 is a non-privileged module

End of enumeration elements list.

EPWM1 : Set EPWM1 to Non-privileged State
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

EPWM1 is a privileged module (default)

#1 : 1

EPWM1 is a non-privileged module

End of enumeration elements list.

BPWM0 : Set BPWM0 to Non-privileged State
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM0 is a privileged module (default)

#1 : 1

BPWM0 is a non-privileged module

End of enumeration elements list.

BPWM1 : Set BPWM1 to Non-privileged State
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM1 is a privileged module (default)

#1 : 1

BPWM1 is a non-privileged module

End of enumeration elements list.

SCU_PNPSET3 (PNPSET3)

Peripheral Non-privileged Attribution Set Register3 (0x4006_0000~0x4007_FFFF)
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QSPI0 : Set QSPI0 to Non-privileged State
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

QSPI0 is a privileged module (default)

#1 : 1

QSPI0 is a non-privileged module

End of enumeration elements list.

SPI0 : Set SPI0 to Non-privileged State
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 is a privileged module (default)

#1 : 1

SPI0 is a non-privileged module

End of enumeration elements list.

SPI1 : Set SPI1 to Non-privileged State
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI1 is a privileged module (default)

#1 : 1

SPI1 is a non-privileged module

End of enumeration elements list.

SPI2 : Set SPI2 to Non-privileged State
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI2 is a privileged module (default)

#1 : 1

SPI2 is a non-privileged module

End of enumeration elements list.

SPI3 : Set SPI3 to Non-privileged State
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI3 is a privileged module (default)

#1 : 1

SPI3 is a non-privileged module

End of enumeration elements list.

UART0 : Set UART0 to Non-privileged State
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 is a privileged module (default)

#1 : 1

UART0 is a non-privileged module

End of enumeration elements list.

UART1 : Set UART1 to Non-privileged State
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 is a privileged module (default)

#1 : 1

UART1 is a non-privileged module

End of enumeration elements list.

UART2 : Set UART2 to Non-privileged State
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART2 is a privileged module (default)

#1 : 1

UART2 is a non-privileged module

End of enumeration elements list.

UART3 : Set UART3 to Non-privileged State
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART3 is a privileged module (default)

#1 : 1

UART3 is a non-privileged module

End of enumeration elements list.

UART4 : Set UART4 to Non-privileged State
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART4 is a privileged module (default)

#1 : 1

UART4 is a non-privileged module

End of enumeration elements list.

UART5 : Set UART5 to Non-privileged State
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART5 is a privileged module (default)

#1 : 1

UART5 is a non-privileged module

End of enumeration elements list.

SCU_PNPSET4 (PNPSET4)

Peripheral Non-privileged Attribution Set Register4 (0x4008_0000~0x4009_FFFF)
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0 : Set I2C0 to Non-privileged State
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 is a privileged module (default)

#1 : 1

I2C0 is a non-privileged module

End of enumeration elements list.

I2C1 : Set I2C1 to Non-privileged State
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 is a privileged module (default)

#1 : 1

I2C1 is a non-privileged module

End of enumeration elements list.

I2C2 : Set I2C2 to Non-privileged State
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C2 is a privileged module (default)

#1 : 1

I2C2 is a non-privileged module

End of enumeration elements list.

SC0 : Set SC0 to Non-privileged State
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC0 is a privileged module (default)

#1 : 1

SC0 is a non-privileged module

End of enumeration elements list.

SC1 : Set SC1 to Non-privileged State
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC1 is a privileged module (default)

#1 : 1

SC1 is a non-privileged module

End of enumeration elements list.

SC2 : Set SC2 to Non-privileged State
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC2 is a privileged module (default)

#1 : 1

SC2 is a non-privileged module

End of enumeration elements list.

SCU_PNPSET5 (PNPSET5)

Peripheral Non-privileged Attribution Set Register5 (0x400A_0000~0x400B_FFFF)
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0 : Set CAN0 to Non-privileged State
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

CAN0 is a privileged module (default)

#1 : 1

CAN0 is a non-privileged module

End of enumeration elements list.

QEI0 : Set QEI0 to Non-privileged State
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

QEI0 is a privileged module (default)

#1 : 1

QEI0 is a non-privileged module

End of enumeration elements list.

QEI1 : Set QEI1 to Non-privileged State
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

QEI1 is a privileged module (default)

#1 : 1

QEI1 is a non-privileged module

End of enumeration elements list.

ECAP0 : Set ECAP0 to Non-privileged State
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

ECAP0 is a privileged module (default)

#1 : 1

ECAP0 is a non-privileged module

End of enumeration elements list.

ECAP1 : Set ECAP1 to Non-privileged State
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

ECAP1 is a privileged module (default)

#1 : 1

ECAP1 is a non-privileged module

End of enumeration elements list.

TRNG : Set TRNG to Non-privileged State
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

TRNG is a privileged module (default)

#1 : 1

TRNG is a non-privileged module

End of enumeration elements list.

LCD : Set LCD to Non-privileged State
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

LCD is a privileged module (default)

#1 : 1

LCD is a non-privileged module

End of enumeration elements list.

TAMPER : Set TAMPER to Non-privileged State
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

TAMPER is a privileged module (default)

#1 : 1

TAMPER is a non-privileged module

End of enumeration elements list.

SCU_PNPSET6 (PNPSET6)

Peripheral Non-privileged Attribution Set Register6 (0x400C_0000~0x400D_FFFF)
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD : Set USBD to Non-privileged State
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

USBD is a privileged module (default)

#1 : 1

USBD is a non-privileged module

End of enumeration elements list.

USCI0 : Set USCI0 to Non-privileged State
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

USCI0 is a privileged module (default)

#1 : 1

USCI0 is a non-privileged module

End of enumeration elements list.

USCI1 : Set USCI1 to Non-privileged State
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

USCI1 is a privileged module (default)

#1 : 1

USCI1 is a non-privileged module

End of enumeration elements list.

SCU_IONPSET (IONPSET)

I/O Non-privileged Attribution Set Register
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA : Set GPIO Port a to Non-privileged State
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port A is privileged (default)

#1 : 1

GPIO port A is non-privileged

End of enumeration elements list.

PB : Set GPIO Port B to Non-privileged State
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port B is privileged (default)

#1 : 1

GPIO port B is non-privileged

End of enumeration elements list.

PC : Set GPIO Port C to Non-privileged State
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port C is privileged (default)

#1 : 1

GPIO port C is non-privileged

End of enumeration elements list.

PD : Set GPIO Port D to Non-privileged State
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port D is privileged (default)

#1 : 1

GPIO port D is non-privileged

End of enumeration elements list.

PE : Set GPIO Port E to Non-privileged State
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port E is privileged (default)

#1 : 1

GPIO port E is non-privileged

End of enumeration elements list.

PF : Set GPIO Port F to Non-privileged State
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port F is privileged (default)

#1 : 1

GPIO port F is non-privileged

End of enumeration elements list.

PG : Set GPIO Port G to Non-privileged State
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port G is privileged (default)

#1 : 1

GPIO port G is non-privileged

End of enumeration elements list.

PH : Set GPIO Port H to Non-privileged State
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port H is privileged (default)

#1 : 1

GPIO port H is non-privileged

End of enumeration elements list.

SCU_SRAMNPSET (SRAMNPSET)

SRAM Non-privileged Attribution Set Register
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECn : Set SRAM Section n to Non-privileged State Size per section is 16 Kbytes. Secure SRAM section n is 0x2000_0000+0x4000*n to 0x2000_0000+0x4000*(n+1)-0x1 Non-secure SRAM section n is 0x3000_0000+0x4000*n to 0x3000_0000+0x4000*(n+1)-0x1
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

SRAM Section n is privileged (default)

1 : 1

SRAM Section n is non-privileged

End of enumeration elements list.

SCU_MEMNPSET (MEMNPSET)

Other Memory Non-privileged Attribution Set Register
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASH : Set Flash to Non-privileged State Set the privileged state of memory ranging from 0x0000_0000 to 0x1FFF_FFFF.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Flash is set to privileged (default)

#1 : 1

Flash is set to non-privileged

End of enumeration elements list.

EXTMEM : Set External Memory (EBI Memory) to Non-privileged State Set the privileged state of memory ranging from 0x6000_0000 to 0x7FFF_FFFF.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

External Memory is set to privileged (default)

#1 : 1

External Memory is set to non-privileged

End of enumeration elements list.

SCU_PVIOIEN (PVIOIEN)

Privileged Violation Interrupt Enable Register
address_offset : 0x12C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB0IEN : APB0 Privileged Violation Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of APB0 Disabled

#1 : 1

Interrupt triggered from privileged violation of APB0 Enabled

End of enumeration elements list.

APB1IEN : APB1 Privileged Violation Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of APB1 Disabled

#1 : 1

Interrupt triggered from privileged violation of APB1 Enabled

End of enumeration elements list.

GPIOIEN : GPIO Privileged Violation Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of GPIO Disabled

#1 : 1

Interrupt triggered from privileged violation of GPIO Enabled

End of enumeration elements list.

EBIIEN : EBI Privileged Violation Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of EBI Disabled

#1 : 1

Interrupt triggered from privileged violation of EBI Enabled

End of enumeration elements list.

USBHIEN : USBH Privileged Violation Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of USB host Disabled

#1 : 1

Interrupt triggered from privileged violation of USB host Enabled

End of enumeration elements list.

CRCIEN : CRC Privileged Violation Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of CRC Disabled

#1 : 1

Interrupt triggered from privileged violation of CRC Enabled

End of enumeration elements list.

SDH0IEN : SDH0 Privileged Violation Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of SD host 0 Disabled

#1 : 1

Interrupt triggered from privileged violation of SD host 0 Enabled

End of enumeration elements list.

PDMA0IEN : PDMA0 Privileged Violation Interrupt Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of PDMA0 Disabled

#1 : 1

Interrupt triggered from privileged violation of PDMA0 Enabled

End of enumeration elements list.

PDMA1IEN : PDMA1 Privileged Violation Interrupt Enable Bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of PDMA1 Disabled

#1 : 1

Interrupt triggered from privileged violation of PDMA1 Enabled

End of enumeration elements list.

SRAM0IEN : SRAM Bank 0 Privileged Violation Interrupt Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of SRAM bank0 Disabled

#1 : 1

Interrupt triggered from privileged violation of SRAM bank0 Enabled

End of enumeration elements list.

SRAM1IEN : SRAM Bank 1 Privileged Violation Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of SRAM bank1 Disabled

#1 : 1

Interrupt triggered from privileged violation of SRAM bank1 Enabled

End of enumeration elements list.

FMCIEN : FMC Privileged Violation Interrupt Enable Bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of FMC Disabled

#1 : 1

Interrupt triggered from privileged violation of FMC Enabled

End of enumeration elements list.

FLASHIEN : FLASH Privileged Violation Interrupt Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of Flash data Disabled

#1 : 1

Interrupt triggered from privileged violation of Flash data Enabled

End of enumeration elements list.

SCUIEN : SCU Privileged Violation Interrupt Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of SCU Disabled

#1 : 1

Interrupt triggered from privileged violation of SCU Enabled

End of enumeration elements list.

SYSIEN : SYS Privileged Violation Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of system manager Disabled

#1 : 1

Interrupt triggered from privileged violation of system manager Enabled

End of enumeration elements list.

CRPTIEN : CRPT Privileged Violation Interrupt Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of crypto Disabled

#1 : 1

Interrupt triggered from privileged violation of crypto Enabled

End of enumeration elements list.

KSIEN : KS Privileged Violation Interrupt Enable Bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of keystore Disabled

#1 : 1

Interrupt triggered from privileged violation of keystore Enabled

End of enumeration elements list.

SRAM2IEN : SRAM2 Privileged Violation Interrupt Enable Bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from privileged violation of SRAM2 Disabled

#1 : 1

Interrupt triggered from privileged violation of SRAM2 Enabled

End of enumeration elements list.

SCU_PVINTSTS (PVINTSTS)

Privileged Violation Interrupt Status Register
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB0IF : APB0 Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No APB0 violation interrupt event

#1 : 1

There is APB0 violation interrupt event

End of enumeration elements list.

APB1IF : APB1 Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No APB1 violation interrupt event

#1 : 1

There is APB1 violation interrupt event

End of enumeration elements list.

GPIOIF : GPIO Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No GPIO violation interrupt event

#1 : 1

There is GPIO violation interrupt event

End of enumeration elements list.

EBIIF : EBI Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No EBI violation interrupt event

#1 : 1

There is EBI violation interrupt event

End of enumeration elements list.

USBHIF : USBH Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No USBH violation interrupt event

#1 : 1

There is USBH violation interrupt event

End of enumeration elements list.

CRCIF : CRC Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No CRC violation interrupt event

#1 : 1

There is CRC violation interrupt event

End of enumeration elements list.

SDH0IF : SDH0 Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SDH0 violation interrupt event

#1 : 1

There is SDH0 violation interrupt event

End of enumeration elements list.

PDMA0IF : PDMA0 Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

No PDMA0 violation interrupt event

#1 : 1

There is PDMA0 violation interrupt event

End of enumeration elements list.

PDMA1IF : PDMA1 Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

No PDMA1 violation interrupt event

#1 : 1

There is PDMA1 violation interrupt event

End of enumeration elements list.

SRAM0IF : SRAM0 Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SRAM0 violation interrupt event

#1 : 1

There is SRAM0 violation interrupt event

End of enumeration elements list.

SRAM1IF : SRAM Bank 1 Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SRAM1 violation interrupt event

#1 : 1

There is SRAM1 violation interrupt event

End of enumeration elements list.

FMCIF : FMC Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

No FMC violation interrupt event

#1 : 1

There is FMC violation interrupt event

End of enumeration elements list.

FLASHIF : FLASH Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

No FLASH violation interrupt event

#1 : 1

There is FLASH violation interrupt event

End of enumeration elements list.

SCUIF : SCU Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SCU violation interrupt event

#1 : 1

There is SCU violation interrupt event

End of enumeration elements list.

SYSIF : SYS Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SYS violation interrupt event

#1 : 1

There is SYS violation interrupt event

End of enumeration elements list.

CRPTIF : CRPT Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

No CRPT violation interrupt event

#1 : 1

There is CRPT violation interrupt event

End of enumeration elements list.

KSIF : KS Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

No KS violation interrupt event

#1 : 1

There is KS violation interrupt event

End of enumeration elements list.

SRAM2IF : SRAM Bank 2 Privileged Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SRAM Bank 2 violation interrupt event

#1 : 1

There is SRAM Bank 2 violation interrupt event

End of enumeration elements list.

SCU_SCWP (SCWP)

Security Configuration Write Protection Register
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK : Enable Write Protection Lock Bit (Write One Only) Note: This bit cannot be cleared to 0 without a system-level reset after set to one.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Write protection lock Disabled

#1 : 1

Write protection Enabled and locked

End of enumeration elements list.

WVCODE : Write Verify Code Read operation: Reserved, all zeros. Write operation:
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0x475a : 18266

The write verify code, 0x475A, is needed to do a valid write to SCU_SCWP

End of enumeration elements list.

SCU_PNSSET5 (PNSSET5)

Peripheral Non-secure Attribution Set Register5 (0x400A_0000~0x400B_FFFF)
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0 : Set CAN0 to Non-secure State Write 1 to set CAN0 to non-secure state.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

CAN0 is a secure module (default)

#1 : 1

CAN0 is a non-secure module

End of enumeration elements list.

QEI0 : Set QEI0 to Non-secure State Write 1 to set QEI0 to non-secure state.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

QEI0 is a secure module (default)

#1 : 1

QEI0 is a non-secure module

End of enumeration elements list.

QEI1 : Set QEI1 to Non-secure State Write 1 to set QEI1 to non-secure state.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

QEI1 is a secure module (default)

#1 : 1

QEI1 is a non-secure module

End of enumeration elements list.

ECAP0 : Set ECAP0 to Non-secure State Write 1 to set ECAP0 to non-secure state.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

ECAP0 is a secure module (default)

#1 : 1

ECAP0 is a non-secure module

End of enumeration elements list.

ECAP1 : Set ECAP1 to Non-secure State Write 1 to set ECAP1 to non-secure state.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

ECAP1 is a secure module (default)

#1 : 1

ECAP1 is a non-secure module

End of enumeration elements list.

TRNG : Set TRNG to Non-secure State Write 1 to set TRNG to non-secure state.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

TRNG is a secure module (default)

#1 : 1

TRNG is a non-secure module

End of enumeration elements list.

LCD : Set LCD to Non-secure State Write 1 to set LCD to non-secure state.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

LCD is a secure module (default)

#1 : 1

LCD is a non-secure module

End of enumeration elements list.

SCU_IONSSET0 (IONSSET0)

I/O Non-secure Attribution Set Register0
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA : Set GPIO Port A to Non-secure State Write 1 to set PA to non-secure state. Each bit configures one pin in GPIO port A.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIO port A is secure (default)

1 : 1

GPIO port A is non-secure

End of enumeration elements list.

SCU_IONSSET1 (IONSSET1)

I/O Non-secure Attribution Set Register1
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB : Set GPIO Port B to Non-secure State Write 1 to set PB to non-secure state. Each bit configures one pin in GPIO port B.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIO port B is secure (default)

1 : 1

GPIO port B is non-secure

End of enumeration elements list.

SCU_IONSSET2 (IONSSET2)

I/O Non-secure Attribution Set Register2
address_offset : 0x148 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC : Set GPIO Port C to Non-secure State Write 1 to set PC to non-secure state. Each bit configures one pin in GPIO port C.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIO port C is secure (default)

1 : 1

GPIO port C is non-secure

End of enumeration elements list.

SCU_IONSSET3 (IONSSET3)

I/O Non-secure Attribution Set Register3
address_offset : 0x14C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD : Set GPIO Port D to Non-secure State Write 1 to set PD to non-secure state. Each bit configures one pin in GPIO port D.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIO port D is secure (default)

1 : 1

GPIO port D is non-secure

End of enumeration elements list.

SCU_IONSSET4 (IONSSET4)

I/O Non-secure Attribution Set Register4
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE : Set GPIO Port E to Non-secure State Write 1 to set PE to non-secure state. Each bit configures one pin in GPIO port E.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIO port E is secure (default)

1 : 1

GPIO port E is non-secure

End of enumeration elements list.

SCU_IONSSET5 (IONSSET5)

I/O Non-secure Attribution Set Register5
address_offset : 0x154 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF : Set GPIO Port F to Non-secure State Write 1 to set PF to non-secure state. Each bit configures one pin in GPIO port F.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIO port F is secure (default)

1 : 1

GPIO port F is non-secure

End of enumeration elements list.

SCU_IONSSET6 (IONSSET6)

I/O Non-secure Attribution Set Register6
address_offset : 0x158 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG : Set GPIO Port G to Non-secure State Write 1 to set PG to non-secure state. Each bit configures one pin in GPIO port G.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIO port G is secure (default)

1 : 1

GPIO port G is non-secure

End of enumeration elements list.

SCU_IONSSET7 (IONSSET7)

I/O Non-secure Attribution Set Register7
address_offset : 0x15C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH : Set GPIO Port H to Non-secure State Write 1 to set PH to non-secure state. Each bit configures one pin in GPIO port H.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIO port H is secure (default)

1 : 1

GPIO port H is non-secure

End of enumeration elements list.

SCU_PNSSET6 (PNSSET6)

Peripheral Non-secure Attribution Set Register6 (0x400C_0000~0x400D_FFFF)
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD : Set USBD to Non-secure State Write 1 to set USBD to non-secure state.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

USBD is a secure module (default)

#1 : 1

USBD is a non-secure module

End of enumeration elements list.

USCI0 : Set USCI0 to Non-secure State Write 1 to set USCI0 to non-secure state.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

USCI0 is a secure module (default)

#1 : 1

USCI0 is a non-secure module

End of enumeration elements list.

USCI1 : Set USCI1 to Non-secure State Write 1 to set USCI1 to non-secure state.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

USCI1 is a secure module (default)

#1 : 1

USCI1 is a non-secure module

End of enumeration elements list.

SCU_NSMCTL (NSMCTL)

Non-secure State Monitor Control Register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRESCALE : Pre-scale Value of Non-secure State Monitor Counter
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : 0

Counter Disabled

End of enumeration elements list.

NSMIEN : Non-secure State Monitor Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Non-secure state monitor interrupt Disabled

#1 : 1

Non-secure state monitor interrupt Enabled

End of enumeration elements list.

AUTORLD : Auto Reload Non-secure State Monitor Counter When CURRNS Changing to 1
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable clearing non-secure state monitor counter automatically (default)

#1 : 1

Enable clearing non-secure state monitor counter automatically when the core processor changes from secure state to non-secure state

End of enumeration elements list.

TMRMOD : Non-secure Monitor Mode Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Monitor mode. The counter will count down when the core processor is in non-secure state. (default)

#1 : 1

Free-counting mode. The counter will keep counting no matter the core processor is in secure or non-secure state

End of enumeration elements list.

IDLEON : Monitor Counter Keep Counting When the Chip Is in Idle Mode Enable Bit Note: In monitor mode, the counter is always halted when the core processor is in secure state.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The counter will be halted when the chip is in idle mode

#1 : 1

The counter will keep counting when the chip is in idle mode. (default)

End of enumeration elements list.

DBGON : Monitor Counter Keep Counting When the Chip Is in Debug Mode Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

The counter will be halted when the core processor is halted by ICE. (default)

#1 : 1

The counter will keep counting when the core processor is halted by ICE

End of enumeration elements list.

SCU_NSMLOAD (NSMLOAD)

Non-secure State Monitor Reload Value Register
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RELOAD : Reload Value for Non-secure State Monitor Counter The RELOAD value will be reloaded to the counter whenever the counter counts down to 0.
bits : 0 - 23 (24 bit)
access : read-write

SCU_NSMVAL (NSMVAL)

Non-secure State Monitor Counter Value Register
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VALUE : Counter Value of Non-secure State Monitor Counter A write of any value clears the VALUE to 0 and also clears NSMIF.
bits : 0 - 23 (24 bit)
access : read-write

SCU_NSMSTS (NSMSTS)

Non-secure State Monitor Status Register
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CURRNS : Current Core Processor Secure/Non-secure State (Read Only) Note: This bit can be used to monitor the current secure/non-secure state of the core processor, even if the non-secure state monitor counter is disabled.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Core processor is in secure state

#1 : 1

Core processor is in non-secure state

End of enumeration elements list.

NSMIF : Non-secure State Monitor Interrupt Flag Note: This bit is cleared by writing 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Counter does not count down to 0 since the last NSMIF has been cleared

#1 : 1

Counter counts down to 0

End of enumeration elements list.

SCU_SRAMNSSET (SRAMNSSET)

SRAM Non-secure Attribution Set Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECn : Set SRAM Section n to Non-secure State Write 1 to set SRAM section n to non-secure state. Write 0 is ignored. Size per section is 16 Kbytes. Secure SRAM section n is 0x2000_0000+0x4000*n to 0x2000_0000+0x4000*(n+1)-0x1 Non-secure SRAM section n is 0x3000_0000+0x4000*n to 0x3000_0000+0x4000*(n+1)-0x1
bits : 0 - 14 (15 bit)
access : read-write

Enumeration:

0 : 0

SRAM Section n is secure (default)

1 : 1

SRAM Section n is non-secure

End of enumeration elements list.

SCU_FNSADDR (FNSADDR)

Flash Non-secure Boundary Address Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FNSADDR : Flash Non-secure Boundary Address Indicate the base address of Non-secure region set in user configuration. Refer to FMC section for more details.
bits : 0 - 31 (32 bit)
access : read-only

SCU_SVIOIEN (SVIOIEN)

Security Violation Interrupt Enable Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB0IEN : APB0 Security Violation Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of APB0 Disabled

#1 : 1

Interrupt triggered from security violation of APB0 Enabled

End of enumeration elements list.

APB1IEN : APB1 Security Violation Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of APB1 Disabled

#1 : 1

Interrupt triggered from security violation of APB1 Enabled

End of enumeration elements list.

GPIOIEN : GPIO Security Violation Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of GPIO Disabled

#1 : 1

Interrupt triggered from security violation of GPIO Enabled

End of enumeration elements list.

EBIIEN : EBI Security Violation Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of EBI Disabled

#1 : 1

Interrupt triggered from security violation of EBI Enabled

End of enumeration elements list.

USBHIEN : USBH Security Violation Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of USB host Disabled

#1 : 1

Interrupt triggered from security violation of USB host Enabled

End of enumeration elements list.

CRCIEN : CRC Security Violation Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of CRC Disabled

#1 : 1

Interrupt triggered from security violation of CRC Enabled

End of enumeration elements list.

SDH0IEN : SDH0 Security Violation Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of SD host 0 Disabled

#1 : 1

Interrupt triggered from security violation of SD host 0 Enabled

End of enumeration elements list.

PDMA0IEN : PDMA0 Security Violation Interrupt Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of PDMA0 Disabled

#1 : 1

Interrupt triggered from security violation of PDMA0 Enabled

End of enumeration elements list.

PDMA1IEN : PDMA1 Security Violation Interrupt Enable Bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of PDMA1 Disabled

#1 : 1

Interrupt triggered from security violation of PDMA1 Enabled

End of enumeration elements list.

SRAM0IEN : SRAM Bank 0 Security Violation Interrupt Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of SRAM bank0 Disabled

#1 : 1

Interrupt triggered from security violation of SRAM bank0 Enabled

End of enumeration elements list.

SRAM1IEN : SRAM Bank 1 Security Violation Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of SRAM bank1 Disabled

#1 : 1

Interrupt triggered from security violation of SRAM bank1 Enabled

End of enumeration elements list.

FMCIEN : FMC Security Violation Interrupt Enable Bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of FMC Disabled

#1 : 1

Interrupt triggered from security violation of FMC Enabled

End of enumeration elements list.

FLASHIEN : FLASH Security Violation Interrupt Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of Flash data Disabled

#1 : 1

Interrupt triggered from security violation of Flash data Enabled

End of enumeration elements list.

SCUIEN : SCU Security Violation Interrupt Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of SCU Disabled

#1 : 1

Interrupt triggered from security violation of SCU Enabled

End of enumeration elements list.

SYSIEN : SYS Security Violation Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of system manager Disabled

#1 : 1

Interrupt triggered from security violation of system manager Enabled

End of enumeration elements list.

CRPTIEN : CRPT Security Violation Interrupt Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of crypto Disabled

#1 : 1

Interrupt triggered from security violation of crypto Enabled

End of enumeration elements list.

KSIEN : KS Security Violation Interrupt Enable Bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of keystore Disabled

#1 : 1

Interrupt triggered from security violation of keystore Enabled

End of enumeration elements list.

SRAM2IEN : SRAM2 Security Violation Interrupt Enable Bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of SRAM2 Disabled

#1 : 1

Interrupt triggered from security violation of SRAM2 Enabled

End of enumeration elements list.

SCU_SVINTSTS (SVINTSTS)

Security Violation Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB0IF : APB0 Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No APB0 violation interrupt event

#1 : 1

There is at least a APB0 violation interrupt event

End of enumeration elements list.

APB1IF : APB1 Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No APB1 violation interrupt event

#1 : 1

There is at least a APB1 violation interrupt event

End of enumeration elements list.

GPIOIF : GPIO Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No GPIO violation interrupt event

#1 : 1

There is at least a GPIO violation interrupt event

End of enumeration elements list.

EBIIF : EBI Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No EBI violation interrupt event

#1 : 1

There is at least a EBI violation interrupt event

End of enumeration elements list.

USBHIF : USBH Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No USBH violation interrupt event

#1 : 1

There is at least a USBH violation interrupt event

End of enumeration elements list.

CRCIF : CRC Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No CRC violation interrupt event

#1 : 1

There is at least a CRC violation interrupt event

End of enumeration elements list.

SDH0IF : SDH0 Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SDH0 violation interrupt event

#1 : 1

There is at least a SDH0 violation interrupt event

End of enumeration elements list.

PDMA0IF : PDMA0 Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

No PDMA0 violation interrupt event

#1 : 1

There is at least a PDMA0 violation interrupt event

End of enumeration elements list.

PDMA1IF : PDMA1 Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

No PDMA1 violation interrupt event

#1 : 1

There is at least a PDMA1 violation interrupt event

End of enumeration elements list.

SRAM0IF : SRAM Bank 0 Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SRAM Bank 0 violation interrupt event

#1 : 1

There is at least a SRAM Bank 0 violation interrupt event

End of enumeration elements list.

SRAM1IF : SRAM Bank 1 Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SRAM Bank 1 violation interrupt event

#1 : 1

There is at least a SRAM Bank 1 violation interrupt event

End of enumeration elements list.

FMCIF : FMC Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

No FMC violation interrupt event

#1 : 1

There is at least a FMC violation interrupt event

End of enumeration elements list.

FLASHIF : FLASH Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

No FLASH violation interrupt event

#1 : 1

There is at least a FLASH violation interrupt event

End of enumeration elements list.

SCUIF : SCU Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SCU violation interrupt event

#1 : 1

There is at least a SCU violation interrupt event

End of enumeration elements list.

SYSIF : SYS Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SYS violation interrupt event

#1 : 1

There is at least a SYS violation interrupt event

End of enumeration elements list.

CRPTIF : CRPT Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

No CRPT violation interrupt event

#1 : 1

There is at least a CRPT violation interrupt event

End of enumeration elements list.

KSIF : KS Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

No KS violation interrupt event

#1 : 1

There is at least a KS violation interrupt event

End of enumeration elements list.

SRAM2IF : SRAM Bank 2 Security Violation Interrupt Status Note: Write 1 to clear the interrupt flag.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SRAM Bank 2 violation interrupt event

#1 : 1

There is at least a SRAM Bank 2 violation interrupt event

End of enumeration elements list.

SCU_APB0VSRC (APB0VSRC)

APB0 Security Policy Violation Source
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MASTER : Master Violating Security Policy Indicate which master invokes the security violation. Others is undefined.
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

0x0 : 0

core processor

0x3 : 3

PDMA0

0x4 : 4

SDH0

0x5 : 5

CRYPTO

0x6 : 6

USH

0xb : 11

PDMA1

End of enumeration elements list.

SCU_APB0VA (APB0VA)

APB0 Violation Address
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VIOADDR : Violation Address Indicate the target address of the access, which invokes the security violation.
bits : 0 - 31 (32 bit)
access : read-only

SCU_APB1VSRC (APB1VSRC)

APB1 Security Policy Violation Source
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PNSSET1 (PNSSET1)

Peripheral Non-secure Attribution Set Register1 (0x4002_0000~0x4003_FFFF)
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC : Set CRC to Non-secure State Write 1 to set CRC to non-secure state.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRC is a secure module (default)

#1 : 1

CRC is a non-secure module

End of enumeration elements list.

CRPT : Set CRPT to Non-secure State
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRPT is a secure module (default)

#1 : 1

CRPT is a non-secure module

End of enumeration elements list.

SCU_APB1VA (APB1VA)

APB1 Violation Address
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_GPIOVSRC (GPIOVSRC)

GPIO Security Policy Violation Source
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_GPIOVA (GPIOVA)

GPIO Violation Address
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_EBIVSRC (EBIVSRC)

EBI Security Policy Violation Source
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_EBIVA (EBIVA)

EBI Violation Address
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_USBHVSRC (USBHVSRC)

USBH Security Policy Violation Source
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_USBHVA (USBHVA)

USBH Violation Address
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_CRCVSRC (CRCVSRC)

CRC Security Policy Violation Source
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_CRCVA (CRCVA)

CRC Violation Address
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SD0VSRC (SD0VSRC)

SDH0 Security Policy Violation Source
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SD0VA (SD0VA)

SDH0 Violation Address
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PDMA0VSRC (PDMA0VSRC)

PDMA0 Security Policy Violation Source
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PDMA0VA (PDMA0VA)

PDMA0 Violation Address
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PDMA1VSRC (PDMA1VSRC)

PDMA1 Security Policy Violation Source
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PNSSET2 (PNSSET2)

Peripheral Non-secure Attribution Set Register2 (0x4004_0000~0x4005_FFFF)
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EWDT : Set EWDT to Non-secure State Write 1 to set EWDT to non-secure state.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

EWDT is a secure module (default)

#1 : 1

EWDT is a non-secure module

End of enumeration elements list.

EADC : Set EADC to Non-secure State Write 1 to set EADC to non-secure state.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

EADC is a secure module (default)

#1 : 1

EADC is a non-secure module

End of enumeration elements list.

ACMP01 : Set ACMP01 to Non-secure State Write 1 to set ACMP0, ACMP1 to non-secure state.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

ACMP0, ACMP1 are secure modules (default)

#1 : 1

ACMP0, ACMP1 are non-secure modules

End of enumeration elements list.

DAC : Set DAC to Non-secure State Write 1 to set DAC to non-secure state.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC is a secure module (default)

#1 : 1

DAC is a non-secure module

End of enumeration elements list.

I2S0 : Set I2S0 to Non-secure State Write 1 to set I2S0 to non-secure state.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2S0 is a secure module (default)

#1 : 1

I2S0 is a non-secure module

End of enumeration elements list.

OTG : Set OTG to Non-secure State Write 1 to set OTG to non-secure state.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

OTG is a secure module (default)

#1 : 1

OTG is a non-secure module

End of enumeration elements list.

TMR23 : Set TMR23 to Non-secure State Write 1 to set TMR23 to non-secure state.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

TMR23 is a secure module (default)

#1 : 1

TMR23 is a non-secure module

End of enumeration elements list.

TMR45 : Set TMR45 to Non-secure State Write 1 to set TMR45 to non-secure state.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

TMR45 is a secure module (default)

#1 : 1

TMR45 is a non-secure module

End of enumeration elements list.

EPWM0 : Set EPWM0 to Non-secure State Write 1 to set EPWM0 to non-secure state.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

EPWM0 is a secure module (default)

#1 : 1

EPWM0 is a non-secure module

End of enumeration elements list.

EPWM1 : Set EPWM1 to Non-secure State Write 1 to set EPWM1 to non-secure state.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

EPWM1 is a secure module (default)

#1 : 1

EPWM1 is a non-secure module

End of enumeration elements list.

BPWM0 : Set BPWM0 to Non-secure State Write 1 to set BPWM0 to non-secure state.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM0 is a secure module (default)

#1 : 1

BPWM0 is a non-secure module

End of enumeration elements list.

BPWM1 : Set BPWM1 to Non-secure State Write 1 to set BPWM1 to non-secure state.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM1 is a secure module (default)

#1 : 1

BPWM1 is a non-secure module

End of enumeration elements list.

SCU_PDMA1VA (PDMA1VA)

PDMA1 Violation Address
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SRAM0VSRC (SRAM0VSRC)

SRAM0 Security Policy Violation Source
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SRAM0VA (SRAM0VA)

SRAM0 Violation Address
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SRAM1VSRC (SRAM1VSRC)

SRAM1 Security Policy Violation Source
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SRAM1VA (SRAM1VA)

SRAM1 Violation Address
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_FMCVSRC (FMCVSRC)

FMC Security Policy Violation Source
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_FMCVA (FMCVA)

FMC Violation Address
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_FLASHVSRC (FLASHVSRC)

Flash Security Policy Violation Source
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_FLASHVA (FLASHVA)

Flash Violation Address
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SCUVSRC (SCUVSRC)

SCU Security Policy Violation Source
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SCUVA (SCUVA)

SCU Violation Address
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SYSVSRC (SYSVSRC)

System Security Policy Violation Source
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SYSVA (SYSVA)

System Violation Address
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_CRPTVSRC (CRPTVSRC)

Crypto Security Policy Violation Source
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_CRPTVA (CRPTVA)

Crypto Violation Address
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_KSVSRC (KSVSRC)

KS Security Policy Violation Source
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PNSSET3 (PNSSET3)

Peripheral Non-secure Attribution Set Register3 (0x4006_0000~0x4007_FFFF)
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QSPI0 : Set QSPI0 to Non-secure State Write 1 to set QSPI0 to non-secure state.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

QSPI0 is a secure module (default)

#1 : 1

QSPI0 is a non-secure module

End of enumeration elements list.

SPI0 : Set SPI0 to Non-secure State Write 1 to set SPI0 to non-secure state.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 is a secure module (default)

#1 : 1

SPI0 is a non-secure module

End of enumeration elements list.

SPI1 : Set SPI1 to Non-secure State Write 1 to set SPI1 to non-secure state.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI1 is a secure module (default)

#1 : 1

SPI1 is a non-secure module

End of enumeration elements list.

SPI2 : Set SPI2 to Non-secure State Write 1 to set SPI2 to non-secure state.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI2 is a secure module (default)

#1 : 1

SPI2 is a non-secure module

End of enumeration elements list.

SPI3 : Set SPI3 to Non-secure State Write 1 to set SPI3 to non-secure state.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI3 is a secure module (default)

#1 : 1

SPI3 is a non-secure module

End of enumeration elements list.

UART0 : Set UART0 to Non-secure State Write 1 to set UART0 to non-secure state.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 is a secure module (default)

#1 : 1

UART0 is a non-secure module

End of enumeration elements list.

UART1 : Set UART1 to Non-secure State Write 1 to set UART1 to non-secure state.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 is a secure module (default)

#1 : 1

UART1 is a non-secure module

End of enumeration elements list.

UART2 : Set UART2 to Non-secure State Write 1 to set UART2 to non-secure state.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART2 is a secure module (default)

#1 : 1

UART2 is a non-secure module

End of enumeration elements list.

UART3 : Set UART3 to Non-secure State Write 1 to set UART3 to non-secure state.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART3 is a secure module (default)

#1 : 1

UART3 is a non-secure module

End of enumeration elements list.

UART4 : Set UART4 to Non-secure State Write 1 to set UART4 to non-secure state.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART4 is a secure module (default)

#1 : 1

UART4 is a non-secure module

End of enumeration elements list.

UART5 : Set UART5 to Non-secure State Write 1 to set UART5 to non-secure state.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART5 is a secure module (default)

#1 : 1

UART5 is a non-secure module

End of enumeration elements list.

SCU_KSVA (KSVA)

KS Violation Address
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SRAM2VSRC (SRAM2VSRC)

SRAM2 Security Policy Violation Source
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SRAM2VA (SRAM2VA)

SRAM2 Violation Address
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SINFAEN (SINFAEN)

Shared Information Access Enable Register
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCUSIAEN : SCU Shared Information Access Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Non-secure CPU access SCU Shared information Disabled

#1 : 1

Non-secure CPU access SCU Shared information Enabled

End of enumeration elements list.

SYSSIAEN : SYS Shared Information Access Enable Bit Note: Include clock information.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Non-secure CPU access SYS Shared information Disabled

#1 : 1

Non-secure CPU access SYS Shared information Enabled

End of enumeration elements list.

FMCSIAEN : FMC Shared Information Access Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Non-secure CPU access FMC Shared information Disabled

#1 : 1

Non-secure CPU access FMC Shared information Enabled

End of enumeration elements list.

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SCU

Peripheral Memory Blocks

Registers

SCU_PNSSET0 (PNSSET0)

SCU_PNSSET4 (PNSSET4)

SCU_PNPSET0 (PNPSET0)

SCU_PNPSET1 (PNPSET1)

SCU_PNPSET2 (PNPSET2)

SCU_PNPSET3 (PNPSET3)

SCU_PNPSET4 (PNPSET4)

SCU_PNPSET5 (PNPSET5)

SCU_PNPSET6 (PNPSET6)

SCU_IONPSET (IONPSET)

SCU_SRAMNPSET (SRAMNPSET)

SCU_MEMNPSET (MEMNPSET)

SCU_PVIOIEN (PVIOIEN)

SCU_PVINTSTS (PVINTSTS)

SCU_SCWP (SCWP)

SCU_PNSSET5 (PNSSET5)

SCU_IONSSET0 (IONSSET0)

SCU_IONSSET1 (IONSSET1)

SCU_IONSSET2 (IONSSET2)

SCU_IONSSET3 (IONSSET3)

SCU_IONSSET4 (IONSSET4)

SCU_IONSSET5 (IONSSET5)

SCU_IONSSET6 (IONSSET6)

SCU_IONSSET7 (IONSSET7)

SCU_PNSSET6 (PNSSET6)

SCU_NSMCTL (NSMCTL)

SCU_NSMLOAD (NSMLOAD)

SCU_NSMVAL (NSMVAL)

SCU_NSMSTS (NSMSTS)

SCU_SRAMNSSET (SRAMNSSET)

SCU_FNSADDR (FNSADDR)

SCU_SVIOIEN (SVIOIEN)

SCU_SVINTSTS (SVINTSTS)

SCU_APB0VSRC (APB0VSRC)

SCU_APB0VA (APB0VA)

SCU_APB1VSRC (APB1VSRC)

SCU_PNSSET1 (PNSSET1)

SCU_APB1VA (APB1VA)

SCU_GPIOVSRC (GPIOVSRC)

SCU_GPIOVA (GPIOVA)

SCU_EBIVSRC (EBIVSRC)

SCU_EBIVA (EBIVA)

SCU_USBHVSRC (USBHVSRC)

SCU_USBHVA (USBHVA)

SCU_CRCVSRC (CRCVSRC)

SCU_CRCVA (CRCVA)

SCU_SD0VSRC (SD0VSRC)

SCU_SD0VA (SD0VA)

SCU_PDMA0VSRC (PDMA0VSRC)

SCU_PDMA0VA (PDMA0VA)

SCU_PDMA1VSRC (PDMA1VSRC)

SCU_PNSSET2 (PNSSET2)

SCU_PDMA1VA (PDMA1VA)

SCU_SRAM0VSRC (SRAM0VSRC)

SCU_SRAM0VA (SRAM0VA)

SCU_SRAM1VSRC (SRAM1VSRC)

SCU_SRAM1VA (SRAM1VA)

SCU_FMCVSRC (FMCVSRC)

SCU_FMCVA (FMCVA)

SCU_FLASHVSRC (FLASHVSRC)

SCU_FLASHVA (FLASHVA)

SCU_SCUVSRC (SCUVSRC)

SCU_SCUVA (SCUVA)

SCU_SYSVSRC (SYSVSRC)

SCU_SYSVA (SYSVA)

SCU_CRPTVSRC (CRPTVSRC)

SCU_CRPTVA (CRPTVA)

SCU_KSVSRC (KSVSRC)

SCU_PNSSET3 (PNSSET3)

SCU_KSVA (KSVA)

SCU_SRAM2VSRC (SRAM2VSRC)

SCU_SRAM2VA (SRAM2VA)

SCU_SINFAEN (SINFAEN)