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FMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xD0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

Registers

NS_FMC_ISPCTL

NS_FMC_ISPTRG

NS_FMC_ISPADDR

NS_FMC_ISPSTS

NS_FMC_ISPDAT

NS_FMC_ISPCMD

NS_FMC_XOMR0STS

NS_FMC_XOMR1STS

NS_FMC_XOMR2STS

NS_FMC_XOMR3STS

NS_FMC_XOMSTS


NS_FMC_ISPCTL

Non-secure ISP Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NS_FMC_ISPCTL NS_FMC_ISPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPEN APUEN NS_ISPFF NS_INTEN

ISPEN : ISP Enable Bit (Read Only) ISP function enable. Note: This bit is read only to show ISP function enable.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#1 : 1

ISP function Enabled

End of enumeration elements list.

APUEN : APROM Update Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

APROM cannot be updated when the chip runs in APROM

#1 : 1

APROM can be updated when the chip runs in APROM

End of enumeration elements list.

NS_ISPFF : Non-sec ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: This bit needs to be cleared by writing 1 to it. APROM writes to itself if APUEN is set to 0. Page Erase command at LOCK mode with ICE connection Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands Read any content of boot loader with ICE connection ISP CMD in XOM region, except xom page erase and chksum command The wrong setting of page erase ISP CMD in XOM Violate XOM setting one time protection Page erase ISP CMD in Secure region setting page Page erase, mass erase, multi-word program or 64-bit word program in OTP NS_ISP Conflict Error Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

NS_INTEN : Non-secure ISP Interuppt Enable Bit Note: This bit is write protected. Refer to the SYS_REGLCTL register.Before use INT,user need to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

NS_ISP INT Disabled

#1 : 1

NS_ISP INT Enabled

End of enumeration elements list.


NS_FMC_ISPTRG

Non-secure ISP Trigger Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NS_FMC_ISPTRG NS_FMC_ISPTRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NS_ISPGO

NS_ISPGO : Non-sec ISP Start Trigger (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

ISP operation is finished

#1 : 1

ISP is progressed

End of enumeration elements list.


NS_FMC_ISPADDR

Non-secure ISP Address Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NS_FMC_ISPADDR NS_FMC_ISPADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NS_ISPADDR

NS_ISPADDR : Non-sec ISP Address The M2354 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. For CRC32 Checksum Calculation command, this field is the Flash starting address for checksum calculation, 2 Kbytes alignment is necessary for CRC32 checksum calculation. For Flash32-bit Program, ISP address needs word alignment (4-byte). For Flash 64-bit Program, ISP address needs double word alignment (8-byte). Non-sec ISP address must be active at Non-sec region.
bits : 0 - 31 (32 bit)
access : read-write


NS_FMC_ISPSTS

Non-secure ISP Status Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NS_FMC_ISPSTS NS_FMC_ISPSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NS_ISPBUSY NS_ISPFF ALLONE NSINTFLAG NSISPCER

NS_ISPBUSY : Non-sec ISP Busy Flag (Read Only) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

ISP operation is finished

#1 : 1

ISP is progressed

End of enumeration elements list.

NS_ISPFF : Non-sec ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: This bit needs to be cleared by writing 1 to it. APROM writes to itself if APUEN is set to 0. Page Erase command at LOCK mode with ICE connection Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands Read any content of boot loader with ICE connection ISP CMD in XOM region, except xom page erase and chksum command The wrong setting of page erase ISP CMD in XOM Violate XOM setting one time protection Page erase ISP CMD in Secure region setting page Page erase, mass erase, multi-word program or 64-bit word program in OTP Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

ALLONE : Flash All-one Verification Flag This bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit also can be clear by writing 1
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Flash bits are not all 1 after 'Run Flash All-One Verification' complete

#1 : 1

All of Flash bits are 1 after 'Run Flash All-One Verification' complete

End of enumeration elements list.

NSINTFLAG : Non-sec ISP Interuppt Flag Note: This function needs to be enabled by Non-secure FMC_ISPCTRL[24].
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

ISP Not FinishED

#1 : 1

ISP done or ISPFF set

End of enumeration elements list.

NSISPCER : Non-secure ISP Conflict Error This bit shows when FMC is doing ISP operation.User can not access NS_FMC_ISP_ADDR,NS_FMC_ISPDAT,NS_FMC_ISPCMD,NS_FMC_ISPTRG. It would cause ISPFF.
bits : 28 - 28 (1 bit)
access : read-write


NS_FMC_ISPDAT

Non-secure ISP Data Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NS_FMC_ISPDAT NS_FMC_ISPDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NS_ISPDAT

NS_ISPDAT : Non-sec ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write


NS_FMC_ISPCMD

Non-secure ISP Command Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NS_FMC_ISPCMD NS_FMC_ISPCMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NS_CMD

NS_CMD : Non-sec ISP Command ISP command table is shown below: The other commands are invalid.
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0x00 : 0

FLASH Read

0x04 : 4

Read Unique ID

0x08 : 8

Read Flash All-One Result

0x0b : 11

Read Company ID

0x0c : 12

Read Device ID

0x0d : 13

Read Checksum

0x21 : 33

FLASH 32-bit Program

0x22 : 34

FLASH Page Erase. Erase only non-secure page in two banks

0x28 : 40

Run Flash All-One Verification

0x2d : 45

Run Checksum Calculation

End of enumeration elements list.


NS_FMC_XOMR0STS

Non-secure XOM Region 0 Status Register
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NS_FMC_XOMR0STS NS_FMC_XOMR0STS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE BASE

SIZE : XOM Region 0 Size (Page-aligned) SIZE is the page number of XOM Region 0.
bits : 0 - 7 (8 bit)
access : read-only

BASE : XOM Region 0 Base Address (Page-aligned) BASE is the base address of XOM Region 0.
bits : 8 - 31 (24 bit)
access : read-only


NS_FMC_XOMR1STS

Non-secure XOM Region 1 Status Register
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NS_FMC_XOMR1STS NS_FMC_XOMR1STS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE BASE

SIZE : XOM Region 1 Size (Page-aligned) SIZE is the page number of XOM Region 1.
bits : 0 - 7 (8 bit)
access : read-only

BASE : XOM Region 1 Base Address (Page-aligned) BASE is the base address of XOM Region 1.
bits : 8 - 31 (24 bit)
access : read-only


NS_FMC_XOMR2STS

Non-secure XOM Region 2 Status Register
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NS_FMC_XOMR2STS NS_FMC_XOMR2STS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE BASE

SIZE : XOM Region 2 Size (Page-aligned) SIZE is the page number of XOM Region 2.
bits : 0 - 7 (8 bit)
access : read-only

BASE : XOM Region 2 Base Address (Page-aligned) BASE is the base address of XOM Region 2.
bits : 8 - 31 (24 bit)
access : read-only


NS_FMC_XOMR3STS

Non-secure XOM Region 3 Status Register
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NS_FMC_XOMR3STS NS_FMC_XOMR3STS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE BASE

SIZE : XOM Region 3 Size (Page-aligned) SIZE is the page number of XOM Region 3.
bits : 0 - 7 (8 bit)
access : read-only

BASE : XOM Region 3 Base Address (Page-aligned) BASE is the base address of XOM Region 3.
bits : 8 - 31 (24 bit)
access : read-only


NS_FMC_XOMSTS

Non-secure XOM Status Register
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NS_FMC_XOMSTS NS_FMC_XOMSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOMR0ON XOMR1ON XOMR2ON XOMR3ON XOMPEF

XOMR0ON : XOM Region 0 On XOM Region 0 active status.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

No active

#1 : 1

XOM region 0 is active

End of enumeration elements list.

XOMR1ON : XOM Region 1 On XOM Region 1 active status.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

No active

#1 : 1

XOM region 1 is active

End of enumeration elements list.

XOMR2ON : XOM Region 2 On XOM Region 2 active status.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

No active

#1 : 1

XOM region 2 is active

End of enumeration elements list.

XOMR3ON : XOM Region 3 On XOM Region 3 active status.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

No active

#1 : 1

XOM region 3 is active

End of enumeration elements list.

XOMPEF : XOM Page Erase Function Fail XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Success

#1 : 1

Fail

End of enumeration elements list.



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