Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
PA I/O Mode Control
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE0 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE1 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE2 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE3 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE4 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE5 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE6 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE7 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE8 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE9 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE10 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE11 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE12 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE13 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE14 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE15 : Port A-H I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 3: If MFOS is enabled then GPIO mode setting is ignored.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode (tri-state)
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
PA Pin Value
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIN0 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN1 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN2 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN3 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN4 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN5 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN6 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN7 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN8 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN9 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN10 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN11 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN12 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN13 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN14 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PIN15 : Port A-H Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
The corresponding pin status is low
#1 : 1
The corresponding pin status is high
End of enumeration elements list.
PA De-bounce Enable Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBEN0 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN1 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN2 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN3 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN4 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN5 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN6 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN7 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN8 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN9 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN10 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN11 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN12 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN13 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN14 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN15 : Port A-H Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
PA Interrupt Trigger Type Control
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE0 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE1 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE2 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE3 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE4 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE5 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE6 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE7 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE8 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE9 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE10 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE11 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE12 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE13 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE14 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE15 : Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
PA Interrupt Enable Control Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLIEN0 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN1 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN2 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN3 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN4 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN5 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN6 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN7 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN8 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN9 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN10 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN11 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN12 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN13 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN14 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN15 : Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
RHIEN0 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN1 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN2 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN3 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN4 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN5 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN6 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN7 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN8 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN9 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN10 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN11 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN12 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN13 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN14 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN15 : Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
PA Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTSRC0 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC1 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC2 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC3 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC4 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC5 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC6 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC7 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC8 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC9 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC10 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC11 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC12 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC13 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC14 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC15 : Port A-H Pin[n] Interrupt Source Flag
Write Operation:
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
PA Input Schmitt Trigger Enable Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMTEN0 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN1 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN2 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN3 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN4 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN5 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN6 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN7 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN8 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN9 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN10 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN11 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN12 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN13 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN14 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN15 : Port A-H Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
PA High Slew Rate Control Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSREN0 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN1 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN2 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN3 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN4 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN5 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN6 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN7 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN8 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN9 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN10 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN11 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN12 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN13 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN14 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
HSREN15 : Port A-H Pin[n] High Slew Rate Control
Note 1: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
Note 2: Please refer to the M2354 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Px.n output with fast slew rate mode
#11 : 3
Reserved.
End of enumeration elements list.
PA Pull-up and Pull-down Selection Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUSEL0 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL1 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL2 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL3 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL4 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL5 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL6 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL7 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL8 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL9 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL10 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL11 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL12 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL13 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL14 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PUSEL15 : Port A-H Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
Note 1: Basically, the pull-up control and pull-down control has following behavior limitation.
The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD.
The independent pull-down control register only valid when MODEn set as tri-state mode.
When both pull-uppull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n pull-up and pull-down disabled
#01 : 1
Px.n pull-up enabled
#10 : 2
Px.n pull-down enabled
#11 : 3
Px.n pull-up and pull- down disabled
End of enumeration elements list.
PA Interrupt De-bounce Control Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBCLKSEL : De-bounce Sampling Cycle Selection (Secure only)
Note: These bits are only accessible from the Secure state.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Sample interrupt input once per 1 clocks
#0001 : 1
Sample interrupt input once per 2 clocks
#0010 : 2
Sample interrupt input once per 4 clocks
#0011 : 3
Sample interrupt input once per 8 clocks
#0100 : 4
Sample interrupt input once per 16 clocks
#0101 : 5
Sample interrupt input once per 32 clocks
#0110 : 6
Sample interrupt input once per 64 clocks
#0111 : 7
Sample interrupt input once per 128 clocks
#1000 : 8
Sample interrupt input once per 256 clocks
#1001 : 9
Sample interrupt input once per 2*256 clocks
#1010 : 10
Sample interrupt input once per 4*256 clocks
#1011 : 11
Sample interrupt input once per 8*256 clocks
#1100 : 12
Sample interrupt input once per 16*256 clocks
#1101 : 13
Sample interrupt input once per 32*256 clocks
#1110 : 14
Sample interrupt input once per 64*256 clocks
#1111 : 15
Sample interrupt input once per 128*256 clocks
End of enumeration elements list.
DBCLKSRC : De-bounce Counter Clock Source Selection (Secure only)
Note: This bit is only accessible from the Secure state.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
De-bounce counter clock source is the HCLK
#1 : 1
De-bounce counter clock source is the 32 kHz internal low speed RC oscillator (LIRC)
End of enumeration elements list.
ICLKON : Interrupt Clock on Mode (Secure Only)
Note 3: This bit is only accessible from the Secure state.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1
#1 : 1
All I/O pins edge detection circuit is always active after reset
End of enumeration elements list.
PA Digital Input Path Disable Control
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DINOFF0 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF1 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF2 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF3 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF4 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF5 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF6 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF7 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF8 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF9 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF10 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF11 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF12 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF13 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF14 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF15 : Port A-H Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
PA Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT0 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT1 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT2 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT3 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT4 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT5 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT6 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT7 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT8 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT9 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT10 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT11 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT12 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT13 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT14 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT15 : Port A-H Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
PA Data Output Write Mask
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATMSK0 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK1 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK2 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK3 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK4 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK5 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK6 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK7 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK8 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK9 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK10 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK11 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK12 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK13 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK14 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK15 : Port A-H Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.14/PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
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