TIMER3_CTL

TIMER3_CAP

TIMER3_EXTCTL

TIMER3_EINTSTS

TIMER3_TRGCTL

TIMER3_ALTCTL

TIMER3_CMP

TIMER3_PWMCTL

TIMER3_PWMCLKSRC

TIMER3_PWMCLKPSC

TIMER3_PWMCNTCLR

TIMER3_PWMPERIOD

TIMER3_PWMCMPDAT

TIMER3_PWMDTCTL

TIMER3_PWMCNT

TIMER3_PWMMSKEN

TIMER3_PWMMSK

TIMER3_PWMBNF

TIMER3_PWMFAILBRK

TIMER3_PWMBRKCTL

TIMER3_PWMPOLCTL

TIMER3_PWMPOEN

TIMER3_PWMSWBRK

TIMER3_INTSTS

TIMER3_PWMINTEN0

TIMER3_PWMINTEN1

TIMER3_PWMINTSTS0

TIMER3_PWMINTSTS1

TIMER3_PWMTRGCTL

TIMER3_PWMSCTL

TIMER3_PWMSTATUS

TIMER3_PWMPBUF

TIMER3_PWMCMPBUF

TIMER3_CNT

PSC : Prescale Counter Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
bits : 0 - 7 (8 bit)
access : read-write

FUNCSEL : Function Selection This bit sets the operation mode of Timer4 and Timer5 to PWM function.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTRGEN : Inter-timer Trigger Mode Enable Bit Setting this bit will enable the inter-timer trigger capture function. The Timer0/2/4 will be in event counter mode and counting with external clock source or event.Also, Timer1/3/5 will be in trigger-counting mode of capture function. Note: For Timer1/3/5, this bit is ignored and the read back value is always 0.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PERIOSEL : Periodic Mode Behavior Selection Enable Bit If updated CMPDAT value CNT, CNT will be reset to default value.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TGLPINSEL : Toggle-output Pin Select
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPSRC : Capture Pin Source Selection Note 2: MIRC clock source is only available in Timer4 ~ Timer5.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : Wake-up Function Enable Bit If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EXTCNTEN : Event Counter Mode Enable Bit This bit is for external counting pin function enabled. Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTSTS : Timer Active Status Bit (Read Only) This bit indicates the 24-bit up counter status. Note: This bit may active when CNT 0 transition to CNT 1.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OPMODE : Timer Counting Mode Select
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : Timer Interrupt Enable Bit Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN : Timer Counting Enable Bit Note 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ICEDEBUG : ICE Debug Mode Acknowledge Disable Bit (Write Protect) TIMER counter will keep going no matter CPU is held by ICE or not. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPDAT : Timer Capture Data Register When CAPEN (TIMERx_EXTCTL[3]) bit is set, the transition on the capture source matches the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
bits : 0 - 23 (24 bit)
access : read-only

CNTPHASE : Timer External Count Phase
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEN : Timer Capture Function Enable Bit This bit enables the capture input function.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPFUNCS : Capture Function Selection Note 1: When CAPFUNCS is 0 and CAPIF becomes 1, the current 24-bit timer counter value (CNT value) will be saved to CAPDAT field. Note 2: When CAPFUNCS is 1 and CAPIF becomes 1, the current 24-bit timer counter value (CNT value) will be saved to CAPDAT field then CNT value will be reset immediately.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIEN : Timer Capture Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPDBEN : Timer Capture De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTDBEN : Timer External Counter Pin De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTERCAPSEL : Internal Capture Source Select Note: These bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEDGE : Timer Capture Edge Detect When the first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. Note: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source.
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ECNTSSEL : Event Counter Source Selection to Trigger Event Counter Function
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPDIVSCL : Timer Capture Source Divider Scale These bits indicate the divide scale for capture source divider. Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source.
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF : Timer Capture Interrupt Flag This bit indicates the timer capture interrupt flag status. Note 1: This bit is cleared by writing 1 to it. Note 2: When the CAPEN (TIMERx_EXTCTL[3]) bit is set, the transition on the capture source matches the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, this bit will be set to 1 by hardware. Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the timer will keep register TIMERx_CAP unchanged and drop the new capture value.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGSSEL : Trigger Source Select Bit This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGPWM : Trigger EPWM and BPWM Enable Bit If this bit is set to 1, each timer time-out event or capture event can be as EPWM and BPWM counter clock source.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGEADC : Trigger EADC Enable Bit If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGDAC : Trigger DAC Enable Bit If this bit is set to 1, each timer time-out event or capture event can be triggered DAC.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGPDMA : Trigger PDMA Enable Bit If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FUNCSEL : Function Selection This bit sets the operation mode of Timer0 ~ Timer3 to PWM function. Note 2: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDAT : Timer Comparator Value CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1. Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. Note 2: When timer is operating in continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and use the newest CMPDAT value to be the timer compared value while user writes a new value into the CMPDAT field.
bits : 0 - 23 (24 bit)
access : read-write

CNTEN : PWM Counter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTTYPE : PWM Counter Behavior Type These bits are used to set the count type of Timer0 ~ Timer3. The count type of Timer4 and Timer5 is fixed as the up count type. Note: These bits are not available in Timer4 and Timer5.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE : PWM Counter Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTRLD : Center Re-load In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. Note: This bit is not available in Timer4 and Timer5.
bits : 8 - 8 (1 bit)
access : read-write

IMMLDEN : Immediately Load Enable Bit Note 1: This bit is not available in Timer4 and Timer5. Note 2: If IMMLDEN is enabled, CTRLD will be invalid.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : PWM Wake-up Enable Bit If this bit is set to 1, the Timer4 and Timer5 PWM interrupt event will generate a wake-up trigger event to CPU. Note: This bit is only available in Timer4 and Timer5.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OUTMODE : PWM Output Mode This bit controls the output mode of corresponding PWM channel. Note: This bit is not available in Timer4 and Timer5.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGHALT : ICE Debug Mode Counter Halt (Write Protect) If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGTRIOFF : ICE Debug Mode Acknowledge Disable Bit (Write Protect) PWM output pin will keep output no matter ICE debug mode acknowledged or not. Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSRC : PWM Counter Clock Source Select The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event in Timer0 ~ Timer3. Note 1: These bits are not available in Timer4 and Timer5 Note 2: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKPSC : PWM Counter Clock Pre-scale The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source. Note: The valid value is 12-bit TIMERx_PWMCLKPSC[11:0] in Timer0 ~ Timer3, and 8-bit TIMERx_PWMCLKPSC[7:0] in Timer4 and Timer5.
bits : 0 - 11 (12 bit)
access : read-write

CNTCLR : Clear PWM Counter Control Bit It is automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PERIOD : PWM Period Register In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD. In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. In up and down count type: Note 1: The count type of Timer4 and Timer5 is fixed as up count type. Note 2: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type in Timer0 ~ Timer3.
bits : 0 - 15 (16 bit)
access : read-write

CMP : PWM Comparator Register PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger EADC and PDMA to start conversion.
bits : 0 - 15 (16 bit)
access : read-write

DTCNT : Dead-time Counter (Write Protect) The dead-time can be calculated from the following two formulas: Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 0 - 11 (12 bit)
access : read-write

DTEN : Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect) Dead-time insertion function is only active when PWM complementary mode is enabled. If dead-time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay. Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCKSEL : Dead-time Clock Select (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNT : PWM Counter Value Register (Read Only) User can monitor CNT to know the current counter value in 16-bit period counter.
bits : 0 - 15 (16 bit)
access : read-only

DIRF : PWM Counter Direction Indicator Flag (Read Only) Note 1: This indicator flag is used for Timer0 ~ Timer3 only. Note 2: Since the count type of Timer4 ~ Timer5 is fixed as up count, this bit is fixed 0 in Timer4 and Timer5.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MSKEN0 : PWMx_CH0 Output Mask Enable Bit The PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMERx_PWMMSK[0]) data.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN1 : PWMx_CH1 Output Mask Enable Bit The PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMERx_PWMMSK[1]) data.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT0 : PWMx_CH0 Output Mask Data Control Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT1 : PWMx_CH1 Output Mask Data Control Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKNFEN : Brake Pin Noise Filter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKNFSEL : Brake Pin Noise Filter Clock Selection
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKFCNT : Brake Pin Noise Filter Count The fields is used to control the active noise filter sample time.
bits : 4 - 6 (3 bit)
access : read-write

BRKPINV : Brake Pin Detection Control Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKPINSRC : Brake Pin Source Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CSSBRKEN : Clock Security System Detection Trigger PWM Brake Function Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODBRKEN : Brown-out Detection Trigger PWM Brake Function Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RAMBRKEN : SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CORBRKEN : Core Lockup Detection Trigger PWM Brake Function Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPO0EBEN : Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) Note 1: Only internal ACMP0_O signal from low to high will be detected as brake event. Note 2: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPO1EBEN : Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) Note 1: Only internal ACMP1_O signal from low to high will be detected as brake event. Note 2: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKPEEN : Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSEBEN : Enable System Fail As Edge-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPO0LBEN : Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) Note 1: Only internal ACMP0_O signal from low to high will be detected as brake event. Note 2: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPO1LBEN : Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) Note 1: Only internal ACMP1_O signal from low to high will be detected as brake event. Note 2: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKPLEN : Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSLBEN : Enable System Fail As Level-detect Brake Source (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKAEVEN : PWM Brake Action Select for PWMx_CH0 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKAODD : PWM Brake Action Select for PWMx_CH1 (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV0 : PWMx_CH0 Output Pin Polar Control Bit The bit is used to control polarity state of PWMx_CH0 output pin.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV1 : PWMx_CH1 Output Pin Polar Control Bit The bit is used to control polarity state of PWMx_CH1 output pin. Note: This bit is not available in Timer4 and Timer5.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN0 : PWMx_CH0 Output Pin Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN1 : PWMx_CH1 Output Pin Enable Bit Note: This bit is not available in Timer4 and Timer5.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POSEL : PWMx_CH0 Output Pin Select This bit is used to select the output channel of Timer4 and Timer5 PWM. Note: This bit is only available in Timer4 and Timer5.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKETRG : Software Trigger Edge-detect Brake Source (Write Only) (Write Protect) Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will be set to 1 automatically in TIMERx_PWMINTSTS1 register. Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : write-only

BRKLTRG : Software Trigger Level-detect Brake Source (Write Only) (Write Protect) Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will be set to 1 automatically in TIMERx_PWMINTSTS1 register. Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : write-only

TIF : Timer Interrupt Flag This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. Note: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TWKF : Timer Wake-up Flag This bit indicates the interrupt wake-up flag status of timer. Note: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIEN : PWM Zero Point Interrupt Enable Bit Note: This bit is not available in Timer4 and Timer5
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN : PWM Period Point Interrupt Enable Bit Note: In up-down count type, period point means the center point of current PWM period.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN : PWM Compare Up Count Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN : PWM Compare Down Count Interrupt Enable Bit Note: This bit is not available in Timer4 and Timer5
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKEIEN : PWM Edge-detect Brake Interrupt Enable Bit (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKLIEN : PWM Level-detect Brake Interrupt Enable Bit (Write Protect) Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZIF : PWM Zero Point Interrupt Flag This bit is set by hardware when TIMERx_PWM counter reaches 0. Note 1: This bit is not available in Timer4 and Timer5 Note 2: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

PIF : PWM Period Point Interrupt Flag This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. Note 1: In up-down count type, PIF flag means the center point flag of current PWM period. Note 2: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

CMPUIF : PWM Compare Up Count Interrupt Flag This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. Note 1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type. Note 2: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write

CMPDIF : PWM Compare Down Count Interrupt Flag This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP. Note 1: This bit is not available in Timer4 and Timer5 Note 2: If CMP equal to PERIOD, there is no CMPDIF flag in down count type. Note 3: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write

BRKEIF0 : Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) Note 1: This bit is cleared by writing 1 to it. Note 2: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKEIF1 : Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect) Note 1: This bit is cleared by writing 1 to it. Note 2: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKLIF0 : Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) Note 1: This bit is cleared by writing 1 to it. Note 2: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKLIF1 : Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect) Note 1: This bit is cleared by writing 1 to it. Note 2: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKESTS0 : Edge -detect Brake Status of PWMx_CH0 (Read Only) Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BRKESTS1 : Edge-detect Brake Status of PWMx_CH1 (Read Only) Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BRKLSTS0 : Level-detect Brake Status of PWMx_CH0 (Read Only) Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BRKLSTS1 : Level-detect Brake Status of PWMx_CH1 (Read Only) Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TRGSEL : PWM Counter Event Source Select to Trigger Conversion In Timer0 ~ Timer3,
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGEADC : PWM Counter Event Trigger EADC Conversion Enable Bit Note: Set TRGSEL (TIMERx_PWMTRGCTL[2:0]) to select PWM trigger conversion source.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGPDMA : PWM Counter Event Trigger PDMA Conversion Enable Bit Note 1: This bit is only available in Timer4 and Timer5. Note 2: Set TRGSEL (TIMERx_PWMTRGCTL[2:0]) to select PWM trigger conversion source.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYNCMODE : PWM Synchronous Mode Enable Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYNCSRC : PWM Synchronous Counter Start/Clear Source Select Note 1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0. Note 2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMAXF : PWM Counter Equal to 0xFFFF Flag Note: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKF : PWM Wake-up Flag Note 1: This bit is only available in Timer4 and Timer5. Note 2: This bit is cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EADCTRGF : Trigger EADC Start Conversion Flag Note: This bit is cleared by writing 1 to it.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMATRGF : Trigger PDMA Start Conversion Flag Note 1: This bit is only available in Timer4 and Timer5. Note 2: This bit is cleared by writing 1 to it.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBUF : PWM Period Buffer Register (Read Only) Used as PERIOD active register.
bits : 0 - 15 (16 bit)
access : read-only

CMPBUF : PWM Comparator Buffer Register (Read Only) Used as CMP active register.
bits : 0 - 15 (16 bit)
access : read-only

CNT : Timer Data Register Read operation. Read this register to get CNT value. For example: If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value. If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value. Write operation. Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
bits : 0 - 23 (24 bit)
access : read-write

RSTACT : Timer Data Register Reset Active (Read Only) This bit indicates if the counter reset operation active. When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.