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address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
Extra WDT Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTEN : EWDT Time-out Reset Enable Bit (Write Protect)
Setting this bit will enable the EWDT time-out reset function if the EWDT up counter value has not been cleared after the specific EWDT reset delay period expires.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EWDT time-out reset function Disabled
#1 : 1
EWDT time-out reset function Enabled
End of enumeration elements list.
RSTF : EWDT Time-out Reset Flag
This bit indicates the system has been reset by EWDT time-out reset or not.
Note: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
EWDT time-out reset did not occur
#1 : 1
EWDT time-out reset occurred
End of enumeration elements list.
IF : EWDT Time-out Interrupt Flag
This bit will set to 1 while EWDT up counter value reaches the selected EWDT time-out interval
Note: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EWDT time-out interrupt did not occur
#1 : 1
EWDT time-out interrupt occurred
End of enumeration elements list.
WKEN : WDT Time-out Wake-up Function Control (Write Protect)
If this bit is set to 1, while EWDT time-out interrupt flag IF (EWDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (EWDT_CTL[6]) is enabled, the EWDT time-out interrupt signal will generate a wake-up trigger event to chip.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Chip can be woken up by EWDT time-out interrupt signal generated only if EWDT clock source is selected to 32 kHz internal low speed RC oscillator (LIRC) or LXT.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up trigger event Disabled if EWDT time-out interrupt signal generated
#1 : 1
Wake-up trigger event Enabled if EWDT time-out interrupt signal generated
End of enumeration elements list.
WKF : WDT Time-out Wake-up Flag
This bit indicates the interrupt wake-up flag status of EWDT
Note: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
EWDT does not cause chip wake-up
#1 : 1
Chip wake-up from Idle or Power-down mode if EWDT time-out interrupt signal generated
End of enumeration elements list.
INTEN : EWDT Time-out Interrupt Enable Bit (Write Protect)
If this bit is enabled, the EWDT time-out interrupt signal is generated and inform to CPU.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
EWDT time-out interrupt Disabled
#1 : 1
EWDT time-out interrupt Enabled
End of enumeration elements list.
WDTEN : WDT Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
EWDT Disabled (this action will reset the internal up counter value)
#1 : 1
EWDT Enabled
End of enumeration elements list.
TOUTSEL : WDT Time-out Interval Selection (Write Protect)
These three bits select the time-out interval period for the WDT.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
24 * EWDT_CLK
#0001 : 1
26 * EWDT_CLK
#0010 : 2
28 * EWDT_CLK
#0011 : 3
210 * EWDT_CLK
#0100 : 4
212 * EWDT_CLK
#0101 : 5
214 * EWDT_CLK
#0110 : 6
216 * EWDT_CLK
#0111 : 7
218 * EWDT_CLK
#1000 : 8
220 * EWDT_CLK
End of enumeration elements list.
SYNC : EWDT Enable Control SYNC Flag Indicator (Read Only)
If user executes enable/disable WDTEN (EWDT_CTL[7]), this flag can indicate enable/disable WDTEN function is completed or not.
Note: Performing enable or disable WDTEN bit needs 2 * EWDT_CLK period to become active.
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
Set WDTEN bit is completed
#1 : 1
Set WDTEN bit is synchronizing and not become active yet
End of enumeration elements list.
ICEDEBUG : ICE Debug Mode Acknowledge Disable Bit (Write Protect)
EWDT up counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement affects EWDT counting
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
Extra WDT Alternative Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTDSEL : WDT Reset Delay Selection (Write Protect)
When EWDT time-out happened, user has a time named EWDT Reset Delay Period to clear EWDT counter by programming 0x5AA5 to RSTCNT to prevent EWDT time-out reset happened.
User can select a suitable setting of RSTDSEL for different EWDT Reset Delay Period.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This register will be reset to 0 if EWDT time-out reset happened.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
EWDT Reset Delay Period is 1026 * EWDT_CLK
#01 : 1
EWDT Reset Delay Period is 130 * EWDT_CLK
#10 : 2
EWDT Reset Delay Period is 18 * EWDT_CLK
#11 : 3
EWDT Reset Delay Period is 3 * EWDT_CLK
End of enumeration elements list.
Extra WDT Reset Counter Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RSTCNT : WDT Reset Counter Register
Writing 0x00005AA5 to this field will reset the internal 20-bit EWDT up counter value to 0.
Note: Performing RSTCNT to reset counter needs 2 * EWDT_CLK period to become active.
bits : 0 - 31 (32 bit)
access : write-only
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