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EWWDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

EWWDT_RLDCNT (RLDCNT)

EWWDT_CTL (CTL)

EWWDT_STATUS (STATUS)

EWWDT_CNT (CNT)


EWWDT_RLDCNT (RLDCNT)

Extra WWDT Reload Counter Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EWWDT_RLDCNT EWWDT_RLDCNT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT

RLDCNT : EWWDT Reload Counter Register Writing 0x00005AA5 to this register will reload the EWWDT counter value to 0x3F. Note: User can only write EWWDT_RLDCNT register to reload EWWDT counter value when current EWWDT counter value between 0 and CMPDAT (EWWDT_CTL[21:16]). If user writes EWWDT_RLDCNT when current EWWDT counter value is larger than CMPDAT, EWWDT reset signal will be generated.
bits : 0 - 31 (32 bit)
access : write-only


EWWDT_CTL (CTL)

Extra WWDT Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EWWDT_CTL EWWDT_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDTEN INTEN PSCSEL CMPDAT ICEDEBUG

WWDTEN : EWWDT Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

EWWDT counter is stopped

#1 : 1

EWWDT counter starts counting

End of enumeration elements list.

INTEN : EWWDT Interrupt Enable Bit If this bit is enabled, the EWWDT counter compare match interrupt signal is generated and inform to CPU.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

EWWDT counter compare match interrupt Disabled

#1 : 1

EWWDT counter compare match interrupt Enabled

End of enumeration elements list.

PSCSEL : EWWDT Counter Prescale Period Selection
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Pre-scale is 1 Max time-out period is 1 * 64 * EWWDT_CLK

#0001 : 1

Pre-scale is 2 Max time-out period is 2 * 64 * EWWDT_CLK

#0010 : 2

Pre-scale is 4 Max time-out period is 4 * 64 * EWWDT_CLK

#0011 : 3

Pre-scale is 8 Max time-out period is 8 * 64 * EWWDT_CLK

#0100 : 4

Pre-scale is 16 Max time-out period is 16 * 64 * EWWDT_CLK

#0101 : 5

Pre-scale is 32 Max time-out period is 32 * 64 * EWWDT_CLK

#0110 : 6

Pre-scale is 64 Max time-out period is 64 * 64 * EWWDT_CLK

#0111 : 7

Pre-scale is 128 Max time-out period is 128 * 64 * EWWDT_CLK

#1000 : 8

Pre-scale is 192 Max time-out period is 192 * 64 * EWWDT_CLK

#1001 : 9

Pre-scale is 256 Max time-out period is 256 * 64 * EWWDT_CLK

#1010 : 10

Pre-scale is 384 Max time-out period is 384 * 64 * EWWDT_CLK

#1011 : 11

Pre-scale is 512 Max time-out period is 512 * 64 * EWWDT_CLK

#1100 : 12

Pre-scale is 768 Max time-out period is 768 * 64 * EWWDT_CLK

#1101 : 13

Pre-scale is 1024 Max time-out period is 1024 * 64 * EWWDT_CLK

#1110 : 14

Pre-scale is 1536 Max time-out period is 1536 * 64 * EWWDT_CLK

#1111 : 15

Pre-scale is 2048 Max time-out period is 2048 * 64 * EWWDT_CLK

End of enumeration elements list.

CMPDAT : EWWDT Window Compare Register Set this register to adjust the valid reload window. Note: User can only write EWWDT_RLDCNT register to reload EWWDT counter value when the current EWWDT counter value is between 0 and CMPDAT. If user writes EWWDT_RLDCNT register when the current EWWDT counter value is greater than CMPDAT, EWWDT reset signal will be generated.
bits : 16 - 21 (6 bit)
access : read-write

ICEDEBUG : ICE Debug Mode Acknowledge Disable Bit Note: EWWDT down counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode acknowledgement effects EWWDT counting

#1 : 1

ICE debug mode acknowledgement Disabled

End of enumeration elements list.


EWWDT_STATUS (STATUS)

Extra WWDT Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EWWDT_STATUS EWWDT_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDTIF WWDTRF

WWDTIF : EWWDT Compare Match Interrupt Flag This bit indicates the interrupt flag status of EWWDT while EWWDT counter value matches CMPDAT (EWWDT_CTL[21:16]). Note: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

EWWDT counter value matches CMPDAT

End of enumeration elements list.

WWDTRF : EWWDT Timer-out Reset Flag This bit indicates the system has been reset by EWWDT time-out reset or not. Note: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

EWWDT time-out reset did not occur

#1 : 1

EWWDT time-out reset occurred

End of enumeration elements list.


EWWDT_CNT (CNT)

Extra WWDT Counter Value Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EWWDT_CNT EWWDT_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTDAT

CNTDAT : EWWDT Counter Value CNTDAT will be updated continuously to monitor 6-bit EWWDT down counter value.
bits : 0 - 5 (6 bit)
access : read-only



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