RTC_INIT (INIT)

RTC_CAL (CAL)

RTC_LXTCTL (LXTCTL)

RTC_GPIOCTL0 (GPIOCTL0)

RTC_GPIOCTL1 (GPIOCTL1)

RTC_DSTCTL (DSTCTL)

RTC_TAMPCTL (TAMPCTL)

RTC_TAMPSEED (TAMPSEED)

RTC_TAMPTIME (TAMPTIME)

RTC_TAMPCAL (TAMPCAL)

RTC_CLKFMT (CLKFMT)

RTC_CLKDCTL (CLKDCTL)

RTC_CDBR (CDBR)

RTC_WEEKDAY (WEEKDAY)

RTC_TALM (TALM)

RTC_CALM (CALM)

RTC_LEAPYEAR (LEAPYEAR)

RTC_INTEN (INTEN)

RTC_INTSTS (INTSTS)

RTC_TICK (TICK)

RTC_TAMSK (TAMSK)

RTC_CAMSK (CAMSK)

RTC_SPRCTL (SPRCTL)

RTC_SPR0 (SPR0)

RTC_SPR1 (SPR1)

RTC_SPR2 (SPR2)

RTC_SPR3 (SPR3)

RTC_SPR4 (SPR4)

RTC_SPR5 (SPR5)

RTC_SPR6 (SPR6)

RTC_SPR7 (SPR7)

RTC_SPR8 (SPR8)

RTC_SPR9 (SPR9)

RTC_SPR10 (SPR10)

RTC_SPR11 (SPR11)

RTC_SPR12 (SPR12)

RTC_SPR13 (SPR13)

RTC_SPR14 (SPR14)

RTC_SPR15 (SPR15)

RTC_FREQADJ (FREQADJ)

RTC_SPR16 (SPR16)

RTC_SPR17 (SPR17)

RTC_SPR18 (SPR18)

RTC_SPR19 (SPR19)

RTC_TIME (TIME)

ACTIVE : RTC Active Status (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

INIT : RTC Initiation (Write Only) When RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leave reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. The INIT is a write-only field and read value will be always 0.
bits : 1 - 31 (31 bit)
access : write-only

DAY : 1-Day Calendar Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENDAY : 10-Day Calendar Digit (0~3)
bits : 4 - 5 (2 bit)
access : read-write

MON : 1-Month Calendar Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMON : 10-Month Calendar Digit (0~1)
bits : 12 - 12 (1 bit)
access : read-write

YEAR : 1-Year Calendar Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENYEAR : 10-Year Calendar Digit (0~9)
bits : 20 - 23 (4 bit)
access : read-write

LIRC32KEN : Enable LIRC32K Source
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GAIN : Oscillator Gain Option User can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption.
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

C32KSEL : Clock 32K Source Selection
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCCKSEL : RTC Clock Source Selection
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IOCTLSEL : I/O Pin Backup Control Selection When low speed 32 kHz oscillator is disabled or TAMPxEN is disabled, PF.4 pin (X32_OUT pin), PF.5 pin (X32_IN pin) or PF.6~11 pin (TAMPERx pin) can be used as GPIO function. User can program IOCTLSEL to decide PF.4~11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0/1 control register. Note: IOCTLSEL will automatically be set by hardware to 1 when system power is off and any writable RTC registers has been written at RTCCKEN(CLK_APBCLK0[1]) enabled.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE0 : I/O Operation Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT0 : I/O Output Data
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF0 : I/O Pin Digital Input Path Disable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL0 : I/O Pull-up and Pull-down Enable Bits Determine PF.4 I/O pull-up or pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register is only valid when OPMODE0 is set as input tri-state and open-drain mode.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE1 : I/O Operation Mode
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT1 : I/O Output Data
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF1 : I/O Pin Digital Input Path Disable Bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL1 : I/O Pull-up and Pull-down Enable Bits Determine PF.5 I/O pull-up or pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register is only valid when OPMODE1 is set as input tri-state and open-drain mode.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE2 : I/O Operation Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT2 : I/O Output Data
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF2 : I/O Pin Digital Input Path Disable Bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL2 : I/O Pull-up and Pull-down Enable Bits Determine PF.6 I/O Pull-up or Pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register is only valid when OPMODE2 is set as input tri-state and open-drain mode.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE3 : I/O Operation Mode
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT3 : I/O Output Data
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF3 : I/O Pin Digital Input Path Disable Bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL3 : I/O Pull-up and Pull-down Enable Bits Determine PF.7 I/O pull-up or pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register is only valid when OPMODE3 is set as input tri-state and open-drain mode.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE4 : I/O Operation Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT4 : I/O Output Data
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF4 : I/O Pin Digital Input Path Disable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL4 : I/O Pull-up and Pull-down Enable Bits Determine PF.8 I/O pull-up or pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register is only valid when OPMODE4 is set as input tri-state and open-drain mode.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE5 : I/O Operation Mode
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT5 : I/O Output Data
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF5 : I/O Pin Digital Input Path Disable Bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL5 : I/O Pull-up and Pull-down Enable Bits Determine PF.9 I/O pull-up or pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register is only valid when OPMODE5 is set as input tri-state and open-drain mode.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE6 : I/O Operation Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT6 : I/O Output Data
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF6 : I/O Pin Digital Input Path Disable Bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL6 : I/O Pull-up and Pull-down Enable Bits Determine PF.10 I/O pull-up or pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register is only valid when OPMODE6 is set as input tri-state and open-drain mode.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE7 : I/O Operation Mode
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT7 : I/O Output Data
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF7 : I/O Pin Digital Input Path Disable Bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL7 : I/O Pull-up and Pull-down Enable Bits Determine PF.11 I/O pull-up or pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register is only valid when OPMODE7 is set as input tri-state and open-drain mode.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDHR : Add 1 Hour
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SUBHR : Subtract 1 Hour
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DSBAK : Daylight Saving Back
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYN1ISS : Dynamic Pair 1 Input Source Select This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. Note: This bit is effective only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYN2ISS : Dynamic Pair 2 Input Source Select This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNSRC : Dynamic Reference Pattern This fields determine the new reference pattern when current pattern run out in dynamic pair mode. Note: After this bit is modified, the SEEDRLD (RTC_TAMPCTL[4]) should be set.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEEDRLD : Reload New Seed for PRNG Engine Setting this bit, the tamper configuration will be reloaded. Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. Note 2: The detection reference clock is RTC counter clock. Tamper detector needs to sync 2 ~ 3 RTC counter clock.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNRATE : Dynamic Change Rate This item is choice the dynamic tamper output change rate. Note: After revising this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately.
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0EN : Tamper0 Detect Enable Bit Note: The detection reference clock is RTC counter clock. Tamper detector needs to sync 2 ~ 3 RTC counter clock.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0LV : Tamper 0 Level This bit depends on level attribute of tamper pin for static tamper detection.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0DEN : Tamper 0 De-bounce Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1EN : Tamper 1 Detect Enable Bit Note: The detection reference clock is RTC counter clock. Tamper detector needs to sync 2 ~ 3 RTC counter clock.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1LV : Tamper 1 Level This bit depends on level attribute of tamper pin for static tamper detection.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1DEN : Tamper 1 De-bounce Enable Bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNPR0EN : Dynamic Pair 0 Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2EN : Tamper 2 Detect Enable Bit Note: The detection reference clock is RTC counter clock. Tamper detector need to sync 2 ~ 3 RTC counter clock.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2LV : Tamper 2 Level This bit depends on level attribute of tamper pin for static tamper detection.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2DEN : Tamper 2 De-bounce Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3EN : Tamper 3 Detect Enable Bit Note: The detection reference clock is RTC counter clock. Tamper detector need to sync 2 ~ 3 RTC counter clock.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3LV : Tamper 3 Level This bit depends on level attribute of tamper pin for static tamper detection.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3DEN : Tamper 3 De-bounce Enable Bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNPR1EN : Dynamic Pair 1 Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4EN : Tamper4 Detect Enable Bit Note: The detection reference clock is RTC counter clock. Tamper detector need to sync 2 ~ 3 RTC counter clock.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4LV : Tamper 4 Level This bit depends on level attribute of tamper pin for static tamper detection.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4DEN : Tamper 4 De-bounce Enable Bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5EN : Tamper 5 Detect Enable Bit Note: The detection reference clock is RTC counter clock. Tamper detector need to sync 2 ~ 3 RTC counter clock.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5LV : Tamper 5 Level This bit depends on level attribute of tamper pin for static tamper detection.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5DEN : Tamper 5 De-bounce Enable Bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNPR2EN : Dynamic Pair 2 Enable Bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEED : Seed Value
bits : 0 - 31 (32 bit)
access : read-write

SEC : 1-Sec Time Digit of Tamper Time (0~9)
bits : 0 - 3 (4 bit)
access : read-only

TENSEC : 10-Sec Time Digit of Tamper Time (0~5)
bits : 4 - 6 (3 bit)
access : read-only

MIN : 1-Min Time Digit of Tamper Time (0~9)
bits : 8 - 11 (4 bit)
access : read-only

TENMIN : 10-Min Time Digit of Tamper Time (0~5)
bits : 12 - 14 (3 bit)
access : read-only

HR : 1-Hour Time Digit of Tamper Time (0~9)
bits : 16 - 19 (4 bit)
access : read-only

TENHR : 10-hour Time Digit of Tamper Time (0~2) Note: 24-hour time scale only.
bits : 20 - 21 (2 bit)
access : read-only

DAY : 1-Day Calendar Digit of Tamper Calendar (0~9)
bits : 0 - 3 (4 bit)
access : read-only

TENDAY : 10-Day Calendar Digit of Tamper Calendar (0~3)
bits : 4 - 5 (2 bit)
access : read-only

MON : 1-Month Calendar Digit of Tamper Calendar (0~9)
bits : 8 - 11 (4 bit)
access : read-only

TENMON : 10-Month Calendar Digit of Tamper Calendar (0~1)
bits : 12 - 12 (1 bit)
access : read-only

YEAR : 1-Year Calendar Digit of Tamper Calendar (0~9)
bits : 16 - 19 (4 bit)
access : read-only

TENYEAR : 10-Year Calendar Digit of Tamper Calendar (0~9)
bits : 20 - 23 (4 bit)
access : read-only

_24HEN : 24-hour / 12-hour Time Scale Selection The RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DCOMPEN : Dynamic Compensation Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LXTFDEN : LXT Clock Fail/Stop Detector Enable Bit Note: LXT detector will automatically be disabled when CLKSTIF/CLKFIF flag rises, and resumes after Fail/Stop Flag is cleared.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LXTFSW : LXT Clock Fail Detector Switch LIRC32K Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LXTSTSW : LXT Clock Stop Detector Switch LIRC32K Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWLIRCF : LXT Clock Detector Fail/Stop Switch LIRC32K Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LXTSLOWF : LXT Slower Than LIRC32K Flag (Read Only) Note: LXTSLOWF is valid during CLKSTIF (RTC_INTSTS[25]) or CLKFIF (RTC_INTSTS[24]) rising.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

STOPBD : LXT Clock Stop Frequency Detector Stop Boundary The bits define the stop value of frequency monitor window. When LXT frequency monitor counter lower than STOPBD, the LXT frequency detect Stop interrupt flag will set to 1. Note: The boundary is defined as the maximum value of LXT among 256 LIRC32K clock time.
bits : 0 - 7 (8 bit)
access : read-write

FAILBD : LXT Clock Frequency Detector Fail Boundary The bits define the fail value of frequency monitor window. When LXT frequency monitor counter lower than FAILBD, the LXT frequency detect fail interrupt flag will set to 1. Note: The boundary is defined as the minimum value of LXT among 256 LIRC32K clock time.
bits : 16 - 23 (8 bit)
access : read-write

WEEKDAY : Day of the Week Register
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEC : 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENSEC : 10-Sec Time Digit of Alarm Setting (0~5)
bits : 4 - 6 (3 bit)
access : read-write

MIN : 1-Min Time Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMIN : 10-Min Time Digit of Alarm Setting (0~5)
bits : 12 - 14 (3 bit)
access : read-write

HR : 1-Hour Time Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENHR : 10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
bits : 20 - 21 (2 bit)
access : read-write

DAY : 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENDAY : 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 4 - 5 (2 bit)
access : read-write

MON : 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMON : 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 12 - 12 (1 bit)
access : read-write

YEAR : 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENYEAR : 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 20 - 23 (4 bit)
access : read-write

LEAPYEAR : Leap Year Indication (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ALMIEN : Alarm Interrupt Enable Bit Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICKIEN : Time Tick Interrupt Enable Bit Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0IEN : Tamper 0 Interrupt Enable Bit Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1IEN : Tamper 1 or Pair 0 Interrupt Enable Bit Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2IEN : Tamper 2 Interrupt Enable Bit Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3IEN : Tamper 3 or Pair 1 Interrupt Enable Bit Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4IEN : Tamper 4 Interrupt Enable Bit Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5IEN : Tamper 5 or Pair 2 Interrupt Enable Bit Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKFIEN : LXT Clock Frequency Monitor Fail Interrupt Enable Bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSTIEN : LXT Clock Frequency Monitor Stop Interrupt Enable Bit
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALMIF : RTC Alarm Interrupt Flag Note: Write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICKIF : RTC Time Tick Interrupt Flag Note: Write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0IF : Tamper 0 Interrupt Flag This bit is set when TAMPER0 detected level non-equal TAMP0LV (RTC_TAMPCTL[9]). Note 1: Write 1 to clear this bit. Note 2: This interrupt flag will be generated again when Tamper setting condition is not restoration. Note 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1IF : Tamper 1 or Pair 0 Interrupt Flag This bit is set when TAMPER1 detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) or TAMPER0 and TAMPER1 disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated. Note 1: Write 1 to clear this bit. Note 2: This interrupt flag will be generated again when Tamper setting condition is not restoration. Note 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2IF : Tamper 2 Interrupt Flag This bit is set when TAMPER2 detected level non-equal TAMP2LV (RTC_TAMPCTL[17]). Note 1: Write 1 to clear this bit. Note 2: This interrupt flag will be generated again when Tamper setting condition is not restoration. Note 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3IF : Tamper 3 or Pair 1 Interrupt Flag This bit is set when TAMPER3 detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) or TAMPER2 and TAMPER3 disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated or TAMPER0 and TAMPER3 disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated. Note 1: Write 1 to clear this bit. Note 2: This interrupt flag will be generated again when Tamper setting condition is not restoration. Note 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4IF : Tamper 4 Interrupt Flag This bit is set when TAMPER4 detected level non-equal TAMP4LV (RTC_TAMPCTL[25]). Note 1: Write 1 to clear this bit. Note 2: This interrupt flag will be generated again when Tamper setting condition is not restoration. Note 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5IF : Tamper 5 or Pair 2 Interrupt Flag This bit is set when TAMPER5 detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) or TAMPER4 and TAMPER5 disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated or TAMPER0 and TAMPER5 disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated. Note 1: Write 1 to clear this bit. Note 2: This interrupt flag will be generated again when Tamper setting condition is not restoration. Note 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKFIF : LXT Clock Frequency Monitor Fail Interrupt Flag Note 1: Write 1 to clear the bit to 0. Note 2: LXT detector will automatically disable when CLKSTIF/CLKFIF flag rise, resume after Fail/Stop Flag clear.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSTIF : LXT Clock Frequency Monitor Stop Interrupt Flag Note 1: Write 1 to clear the bit to 0. Note 2: LXT detector will automatically disable when CLKSTIF/CLKFIF flag rise, resume after Fail/Stop Flag clear.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICK : Time Tick Register These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSEC : Mask 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write

MTENSEC : Mask 10-Sec Time Digit of Alarm Setting (0~5)
bits : 1 - 1 (1 bit)
access : read-write

MMIN : Mask 1-Min Time Digit of Alarm Setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write

MTENMIN : Mask 10-Min Time Digit of Alarm Setting (0~5)
bits : 3 - 3 (1 bit)
access : read-write

MHR : Mask 1-Hour Time Digit of Alarm Setting (0~9)
bits : 4 - 4 (1 bit)
access : read-write

MTENHR : Mask 10-Hour Time Digit of Alarm Setting (0~2)
bits : 5 - 5 (1 bit)
access : read-write

MDAY : Mask 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write

MTENDAY : Mask 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 1 - 1 (1 bit)
access : read-write

MMON : Mask 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write

MTENMON : Mask 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 3 - 3 (1 bit)
access : read-write

MYEAR : Mask 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 4 - 4 (1 bit)
access : read-write

MTENYEAR : Mask 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 5 - 5 (1 bit)
access : read-write

SPRRWEN : Spare Register Enable Bit Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPRCSTS : SPR Clear Flag This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected. Note 1: Write 1 to clear this bit. Note 2: This bit keeps 1 when RTC_INTSTS[13:8] is not equal to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LXTFCLR : LXT Clock Fail/Stop to Clear Spare Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPARE : Spare Register This field is used to store back-up information defined by user. This field will be cleared by hardware automatically in the following conditions, a tamper pin event is detected, LXT clock fail/stop event occurs if LXTFCLR(RTC_SPRCTL[16]) is 1, or after Flash mass operation.
bits : 0 - 31 (32 bit)
access : read-write