\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x60 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
SPI Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIEN : SPI Transfer Control Enable Bit
In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.
Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer control Disabled
#1 : 1
Transfer control Enabled
End of enumeration elements list.
RXNEG : Receive on Negative Edge
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Received data input signal is latched on the rising edge of SPI bus clock
#1 : 1
Received data input signal is latched on the falling edge of SPI bus clock
End of enumeration elements list.
TXNEG : Transmit on Negative Edge
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#1 : 1
Transmitted data output signal is changed on the falling edge of SPI bus clock
End of enumeration elements list.
CLKPOL : Clock Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI bus clock is idle low
#1 : 1
SPI bus clock is idle high
End of enumeration elements list.
SUSPITV : Suspend Interval
The four bits provide configurable suspend interval between two successive transmit/receive transaction in a Master transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.
(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle
Example:
bits : 4 - 7 (4 bit)
access : read-write
DWIDTH : Data Width
This field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
Note: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically.
bits : 8 - 12 (5 bit)
access : read-write
LSB : Send LSB First
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#1 : 1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
End of enumeration elements list.
HALFDPX : SPI Half-duplex Transfer Enable Bit
This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI operates in full-duplex transfer
#1 : 1
SPI operates in half-duplex transfer
End of enumeration elements list.
RXONLY : Receive-only Mode Enable Bit
This bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive-only mode Disabled
#1 : 1
Receive-only mode Enabled
End of enumeration elements list.
UNITIEN : Unit Transfer Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI unit transfer interrupt Disabled
#1 : 1
SPI unit transfer interrupt Enabled
End of enumeration elements list.
SLAVE : Slave Mode Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
REORDER : Byte Reorder Function Enable Bit
Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Byte Reorder function Disabled
#1 : 1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
End of enumeration elements list.
DATDIR : Data Port Direction Control
This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI data is input direction
#1 : 1
SPI data is output direction
End of enumeration elements list.
SPI FIFO Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRST : Receive Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
End of enumeration elements list.
TXRST : Transmit Reset
Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
End of enumeration elements list.
RXTHIEN : Receive FIFO Threshold Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX FIFO threshold interrupt Disabled
#1 : 1
RX FIFO threshold interrupt Enabled
End of enumeration elements list.
TXTHIEN : Transmit FIFO Threshold Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX FIFO threshold interrupt Disabled
#1 : 1
TX FIFO threshold interrupt Enabled
End of enumeration elements list.
RXTOIEN : Receive Time-out Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive time-out interrupt Disabled
#1 : 1
Receive time-out interrupt Enabled
End of enumeration elements list.
RXOVIEN : Receive FIFO Overrun Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO overrun interrupt Disabled
#1 : 1
Receive FIFO overrun interrupt Enabled
End of enumeration elements list.
TXUFPOL : TX Underflow Data Polarity
Note 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
Note 2: This bit should be set as 0 in I2S mode.
Note 3: When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#1 : 1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
End of enumeration elements list.
TXUFIEN : TX Underflow Interrupt Enable Bit
When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave TX underflow interrupt Disabled
#1 : 1
Slave TX underflow interrupt Enabled
End of enumeration elements list.
RXFBCLR : Receive FIFO Buffer Clear
Note: The RX shift register will not be cleared.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
End of enumeration elements list.
TXFBCLR : Transmit FIFO Buffer Clear
Note: The TX shift register will not be cleared.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
End of enumeration elements list.
SLVBERX : RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error
Note: Slave mode only.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in SPI Slave mode
#1 : 1
Uncompleted RX data will be written into RX FIFO when bit count error event happened in SPI Slave mode. User can read SLVBENUM (SPIx_STATUS2[29:24]) to know the effective bit number of uncompleted RX data when SPI slave bit count error happened
End of enumeration elements list.
RXTH : Receive FIFO Threshold
If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
bits : 24 - 26 (3 bit)
access : read-write
TXTH : Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
bits : 28 - 30 (3 bit)
access : read-write
SPI Status Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSY : Busy Status (Read Only)
Note: By applications, this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF. Therefore the SPI transfer done events of TX/RX operations can be obtained at correct timing point.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
SPI controller is in idle state
#1 : 1
SPI controller is in busy state
End of enumeration elements list.
UNITIF : Unit Transfer Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transaction has been finished since this bit was cleared to 0
#1 : 1
SPI controller has finished one unit transfer
End of enumeration elements list.
SSACTIF : Slave Select Active Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select active interrupt was cleared or not occurred
#1 : 1
Slave select active interrupt event occurred
End of enumeration elements list.
SSINAIF : Slave Select Inactive Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select inactive interrupt was cleared or not occurred
#1 : 1
Slave select inactive interrupt event occurred
End of enumeration elements list.
SSLINE : Slave Select Line Bus Status (Read Only)
Note: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
The slave select line status is 0
#1 : 1
The slave select line status is 1
End of enumeration elements list.
SLVBEIF : Slave Mode Bit Count Error Interrupt Flag
In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Slave mode bit count error event
#1 : 1
Slave mode bit count error event occurred
End of enumeration elements list.
SLVURIF : Slave Mode TX Under Run Interrupt Flag
In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
Note: This bit will be cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Slave TX under run event
#1 : 1
Slave TX under run event occurred
End of enumeration elements list.
RXEMPTY : Receive FIFO Buffer Empty Indicator (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not empty
#1 : 1
Receive FIFO buffer is empty
End of enumeration elements list.
RXFULL : Receive FIFO Buffer Full Indicator (Read Only)
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not full
#1 : 1
Receive FIFO buffer is full
End of enumeration elements list.
RXTHIF : Receive FIFO Threshold Interrupt Flag (Read Only)
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#1 : 1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
End of enumeration elements list.
RXOVIF : Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No FIFO is overrun
#1 : 1
Receive FIFO is overrun
End of enumeration elements list.
RXTOIF : Receive Time-out Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive FIFO time-out event
#1 : 1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
End of enumeration elements list.
SPIENSTS : SPI Enable Status (Read Only)
Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
SPI controller Disabled
#1 : 1
SPI controller Enabled
End of enumeration elements list.
TXEMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not empty
#1 : 1
Transmit FIFO buffer is empty
End of enumeration elements list.
TXFULL : Transmit FIFO Buffer Full Indicator (Read Only)
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not full
#1 : 1
Transmit FIFO buffer is full
End of enumeration elements list.
TXTHIF : Transmit FIFO Threshold Interrupt Flag (Read Only)
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#1 : 1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
End of enumeration elements list.
TXUFIF : TX Underflow Interrupt Flag
When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
Note 1: This bit will be cleared by writing 1 to it.
Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
End of enumeration elements list.
TXRXRST : TX or RX Reset Status (Read Only)
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
The reset function of TXRST or RXRST is done
#1 : 1
Doing the reset function of TXRST or RXRST
End of enumeration elements list.
RXCNT : Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
bits : 24 - 27 (4 bit)
access : read-only
TXCNT : Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
bits : 28 - 31 (4 bit)
access : read-only
SPI Status2 Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLVBENUM : Effective Bit Number of Uncompleted RX Data
This status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode.
This status register will be fixed to 0x0 when SLVBERX (SPIx_FIFOCTL[10]) is disabled.
Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (SPIx_STATUS[6]).
Note 2: Slave mode only.
bits : 24 - 29 (6 bit)
access : read-only
SPI Data Transmit Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.
In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section
Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
bits : 0 - 31 (32 bit)
access : write-only
SPI Data Receive Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register (Read Only)
There are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
bits : 0 - 31 (32 bit)
access : read-only
SPI Clock Divider Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider
The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.
where
is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
Note 1: Not supported in I2S mode.
Note 2: The time interval must be larger than or equal 5 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register.
bits : 0 - 8 (9 bit)
access : read-write
I2S Control Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2SEN : I2S Controller Enable Bit
Note 1: If enabling this bit, I2Sx_BCLK will start to output in Master mode.
Note 2: Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S mode Disabled
#1 : 1
I2S mode Enabled
End of enumeration elements list.
TXEN : Transmit Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data transmit Disabled
#1 : 1
Data transmit Enabled
End of enumeration elements list.
RXEN : Receive Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data receive Disabled
#1 : 1
Data receive Enabled
End of enumeration elements list.
MUTE : Transmit Mute Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data is shifted from buffer
#1 : 1
Transmit channel zero
End of enumeration elements list.
WDWIDTH : Word Width
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
data size is 8-bit
#01 : 1
data size is 16-bit
#10 : 2
data size is 24-bit
#11 : 3
data size is 32-bit
End of enumeration elements list.
MONO : Monaural Data
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data is stereo format
#1 : 1
Data is monaural format
End of enumeration elements list.
ORDER : Stereo Data Order in FIFO
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Left channel data at high byte
#1 : 1
Left channel data at low byte
End of enumeration elements list.
SLAVE : Slave Mode
I2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
MCLKEN : Master Clock Enable Bit
If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master clock Disabled
#1 : 1
Master clock Enabled
End of enumeration elements list.
RZCEN : Right Channel Zero Cross Detection Enable Bit
If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Right channel zero cross detection Disabled
#1 : 1
Right channel zero cross detection Enabled
End of enumeration elements list.
LZCEN : Left Channel Zero Cross Detection Enable Bit
If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Left channel zero cross detection Disabled
#1 : 1
Left channel zero cross detection Enabled
End of enumeration elements list.
RXLCH : Receive Left Channel Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive right channel data in Mono mode
#1 : 1
Receive left channel data in Mono mode
End of enumeration elements list.
RZCIEN : Right Channel Zero Cross Interrupt Enable Bit
Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
LZCIEN : Left Channel Zero Cross Interrupt Enable Bit
Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
FORMAT : Data Format Selection
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
I2S data format
#01 : 1
MSB justified data format
#10 : 2
PCM mode A
#11 : 3
PCM mode B
End of enumeration elements list.
SLVERRIEN : Bit Number Error Interrupt Enable Bit for Slave Mode
Interrupt occurs if this bit is set to 1 and bit number error event occurs.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
I2S Clock Divider Control Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCLKDIV : Master Clock Divider
If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:
where
is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate.
bits : 0 - 6 (7 bit)
access : read-write
BCLKDIV : Bit Clock Divider
The I2S controller will generate bit clock in Master mode. The clock frequency of bit clock , fBCLK, is determined by the following expression:
where
is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by .
The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.
Note: The time interval must be larger than or equal 5 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register.
bits : 8 - 17 (10 bit)
access : read-write
I2SMODE : I2S Clock Divider Number Selection for I2S Mode and SPI Mode
User sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set.
User needs to set I2SMODE before I2SEN (SPIx_I2SCTL[0]) or SPIEN (SPIx_CTL[0]) is enabled.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
The frequency of peripheral clock is set to SPI mode
#1 : 1
The frequency of peripheral clock is set to I2S mode
End of enumeration elements list.
I2SSLAVE : I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode
User sets I2SSLAVE to set frequency of peripheral clock of I2S Master mode and I2S Slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.
I2SSLAVE needs to set before I2SEN (SPIx_I2SCTL[0]) is enabled.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
The frequency of peripheral clock is set to I2S Master mode
#1 : 1
The frequency of peripheral clock is set to I2S Slave mode
End of enumeration elements list.
I2S Status Register
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RIGHT : Right Channel (Read Only)
This bit indicates the current transmit data is belong to which channel.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Left channel
#1 : 1
Right channel
End of enumeration elements list.
RXEMPTY : Receive FIFO Buffer Empty Indicator (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not empty
#1 : 1
Receive FIFO buffer is empty
End of enumeration elements list.
RXFULL : Receive FIFO Buffer Full Indicator (Read Only)
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not full
#1 : 1
Receive FIFO buffer is full
End of enumeration elements list.
RXTHIF : Receive FIFO Threshold Interrupt Flag (Read Only)
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#1 : 1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
End of enumeration elements list.
RXOVIF : Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
bits : 11 - 11 (1 bit)
access : read-write
RXTOIF : Receive Time-out Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive FIFO time-out event
#1 : 1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
End of enumeration elements list.
I2SENSTS : I2S Enable Status (Read Only)
Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
The SPI/I2S control logic is disabled
#1 : 1
The SPI/I2S control logic is enabled
End of enumeration elements list.
TXEMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not empty
#1 : 1
Transmit FIFO buffer is empty
End of enumeration elements list.
TXFULL : Transmit FIFO Buffer Full Indicator (Read Only)
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not full
#1 : 1
Transmit FIFO buffer is full
End of enumeration elements list.
TXTHIF : Transmit FIFO Threshold Interrupt Flag (Read Only)
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#1 : 1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
End of enumeration elements list.
TXUFIF : Transmit FIFO Underflow Interrupt Flag
When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
bits : 19 - 19 (1 bit)
access : read-write
RZCIF : Right Channel Zero Cross Interrupt Flag
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No zero cross event occurred on right channel
#1 : 1
Zero cross event occurred on right channel
End of enumeration elements list.
LZCIF : Left Channel Zero Cross Interrupt Flag
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No zero cross event occurred on left channel
#1 : 1
Zero cross event occurred on left channel
End of enumeration elements list.
SLVERRIF : Bit Number Error Interrupt Flag for Slave Mode
Note: This bit will be cleared by writing 1 to it.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bit number error event occurred
#1 : 1
Bit number error event occurred
End of enumeration elements list.
TXRXRST : TX or RX Reset Status (Read Only)
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
The reset function of TXRST or RXRST is done
#1 : 1
Doing the reset function of TXRST or RXRST
End of enumeration elements list.
RXCNT : Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
bits : 24 - 26 (3 bit)
access : read-only
TXCNT : Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
bits : 28 - 30 (3 bit)
access : read-only
SPI Slave Select Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SS : Slave Selection Control
If AUTOSS bit is cleared to 0,
Note: Master mode only.
Note: Master Mode Only
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
set the SPIx_SS line to inactive state.
Keep the SPIx_SS line at inactive state
#1 : 1
set the SPIx_SS line to active state.
SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2])
End of enumeration elements list.
SSACTPOL : Slave Selection Active Polarity
This bit defines the active polarity of slave selection signal (SPIx_SS).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave selection signal SPIx_SS is active low
#1 : 1
The slave selection signal SPIx_SS is active high
End of enumeration elements list.
AUTOSS : Automatic Slave Selection Function Enable Bit
Note: Master mode only.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0])
#1 : 1
Automatic slave selection function Enabled
End of enumeration elements list.
SLV3WIRE : Slave 3-wire Mode Enable Bit
In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIx_CLK, SPIx_MISO and SPIx_MOSI pins.
Note: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S mode is enabled.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
4-wire bi-direction interface
#1 : 1
3-wire bi-direction interface
End of enumeration elements list.
SLVBEIEN : Slave Mode Bit Count Error Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode bit count error interrupt Disabled
#1 : 1
Slave mode bit count error interrupt Enabled
End of enumeration elements list.
SLVURIEN : Slave Mode TX Under Run Interrupt Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode TX under run interrupt Disabled
#1 : 1
Slave mode TX under run interrupt Enabled
End of enumeration elements list.
SSACTIEN : Slave Select Active Interrupt Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select active interrupt Disabled
#1 : 1
Slave select active interrupt Enabled
End of enumeration elements list.
SSINAIEN : Slave Select Inactive Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select inactive interrupt Disabled
#1 : 1
Slave select inactive interrupt Enabled
End of enumeration elements list.
SPI PDMA Control Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPDMAEN : Transmit PDMA Enable Bit
Note1: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
Note2: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, TX PDMA function cannot be disabled prior to RX PDMA function. User can disable RX PDMA function firstly or disable both functions simultaneously.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit PDMA function Disabled
#1 : 1
Transmit PDMA function Enabled
End of enumeration elements list.
RXPDMAEN : Receive PDMA Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive PDMA function Disabled
#1 : 1
Receive PDMA function Enabled
End of enumeration elements list.
PDMARST : PDMA Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
End of enumeration elements list.
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