Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection :
Key Store Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Key Store Start Control Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No operation
#1 : 1
Start the operation
End of enumeration elements list.
OPMODE : Key Store Operation Mode
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
#000 : 0
Read operation
#001 : 1
Create operation
#010 : 2
Erase one key operation (only for key is in SRAM)
#011 : 3
Erase all keys operation (only for SRAM and Flash)
#100 : 4
Revoke key operation
#101 : 5
Data Remanence prevention operation (only for SRAM)
End of enumeration elements list.
CONT : Read/Write Key Continue Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Read/Write key operation is not continuous to previous operation
#1 : 1
Read/Write key operation is continuous to previous operation
End of enumeration elements list.
INIT : Key Store Initialization
User should to check BUSY(KS_STS[2]) is 0, and then write 1 to this bit and START(KS_CTL[0[), the Key Store will start to be initialized.
After Key Store is initialized, INIT will be cleared.
Note: Before executing INIT, user must check KS(SYS_SRAMPC1) is 00.
bits : 8 - 8 (1 bit)
access : read-write
SILENT : Silent Access Enable Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Silent Access Disabled
#1 : 1
Silent Access Enabled
End of enumeration elements list.
SCMB : Data Scramble Enable Bit
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data Scramble Disabled
#1 : 1
Data Scramble Enabled
End of enumeration elements list.
IEN : Key Store Interrupt Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Key Store Interrupt Disabled
#1 : 1
Key Store Interrupt Enabled
End of enumeration elements list.
Key Store Scramble Key Word 0 Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCMBKEY : Key Store Scramble Key
When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store. If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function.
bits : 0 - 31 (32 bit)
access : read-write
Key Store Scramble Key Word 1 Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Key Store Scramble Key Word 2 Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Key Store Scramble Key Word 3 Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Key Store Entry Key Word 0 Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : Key Data
The register will be cleared if the Key Store executes the write operation or CPU completes the reading key.
bits : 0 - 31 (32 bit)
access : read-write
Key Store Entry Key Word 1 Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Key Store Entry Key Word 2 Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Key Store Entry Key Word 3 Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Key Store Entry Key Word 4 Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Key Store Entry Key Word 5 Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Key Store Entry Key Word 6 Register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Key Store Entry Key Word 7 Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Key Store Metadata Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : Secure Key Selection Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set key as the non-secure key
#1 : 1
Set key as the secure key
End of enumeration elements list.
PRIV : Privilege Key Selection Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set key as the non-privilege key
#1 : 1
Set key as the privilege key
End of enumeration elements list.
READABLE : Key Readable Control Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
key is un-readable
#1 : 1
key is readable
End of enumeration elements list.
RVK : Key Revoke Control Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Key current selected will not be changed
#1 : 1
key current selected will be change to revoked state
End of enumeration elements list.
BS : Booting State Selection Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set key used at all state
#1 : 1
Set key used at boot loader state 1 (BL1 state)
End of enumeration elements list.
SIZE : Key Size Selection Bits
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
#00000 : 0
128 bits
#00001 : 1
163 bits
#00010 : 2
192 bits
#00011 : 3
224 bits
#00100 : 4
233 bits
#00101 : 5
255 bits
#00110 : 6
256 bits
#00111 : 7
283 bits
#01000 : 8
384 bits
#01001 : 9
409 bits
#01010 : 10
512 bits
#01011 : 11
521 bits
#01100 : 12
571 bits
#10000 : 16
1024 bits
#10001 : 17
1536 bits
#10010 : 18
2048 bits
#10011 : 19
3072 bits
#10100 : 20
4096 bits
End of enumeration elements list.
OWNER : Key Owner Selection Bits
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Only for AES used
#001 : 1
Only for HMAC engine used
#010 : 2
Only for RSA engine exponential used (private key)
#011 : 3
Only for RSA engine middle data used
#100 : 4
Only for ECC engine used
#101 : 5
Only for CPU engine use
End of enumeration elements list.
NUMBER : Key Number
Before read or erase one key operation starts, user should write the key number to be operated. When create operation is finished, user can read these bits to get its key number.
bits : 20 - 25 (6 bit)
access : read-write
DST : Key Location Selection Bits
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Key is in SRAM
#01 : 1
Key is in Flash
#10 : 2
Key is in OTP
End of enumeration elements list.
Key Store OTP Keys Status Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
KEY0 : OTP Key 0 Used Status
Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
OTP key 0 is unused
#1 : 1
OTP key 0 is used
End of enumeration elements list.
KEY1 : OTP Key 1 Used Status
Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
OTP key 1 is unused
#1 : 1
OTP key 1 is used
End of enumeration elements list.
KEY2 : OTP Key 2 Used Status
Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
OTP key 2 is unused
#1 : 1
OTP key 2 is used
End of enumeration elements list.
KEY3 : OTP Key 3 Used Status
Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
OTP key 3 is unused
#1 : 1
OTP key 3 is used
End of enumeration elements list.
KEY4 : OTP Key 4 Used Status
Note: If chip is changed to RMA stage, existing key will be revoked after initialization.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
OTP key 4 is unused
#1 : 1
OTP key 4 is used
End of enumeration elements list.
KEY5 : OTP Key 5 Used Status
Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
OTP key 5 is unused
#1 : 1
OTP key 5 is used
End of enumeration elements list.
KEY6 : OTP Key 6 Used Status
Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
OTP key 6 is unused
#1 : 1
OTP key 6 is used
End of enumeration elements list.
KEY7 : OTP Key 7 Used Status
Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
OTP key 7 is unused
#1 : 1
OTP key 7 is used
End of enumeration elements list.
Key Store Remaining Key Count Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RRMKCNT : Key Store SRAM Remaining Key Count
The RRMKCNT shows the remaining key count for SRAM.
bits : 0 - 5 (6 bit)
access : read-only
FRMKCNT : Key Store Flash Remaining Key Count
The FRMKCNT shows the remaining key count for Flash.
bits : 16 - 21 (6 bit)
access : read-only
Key Store Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IF : Key Store Finish Interrupt Flag
This bit is cleared by writing 1 and it has no effect by writing 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Key Store interrupt
#1 : 1
Key Store operation done interrupt
End of enumeration elements list.
EIF : Key Store Error Flag
This bit is cleared by writing 1 and it has no effect by writing 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Key Store error
#1 : 1
Key Store error interrupt
End of enumeration elements list.
BUSY : Key Store Busy Flag (read only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Key Store is idle or finished
#1 : 1
Key Store is busy
End of enumeration elements list.
SRAMFULL : Key Storage at SRAM Full Status Bit (read only)
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Key Storage at SRAM is not full
#1 : 1
Key Storage at SRAM is full
End of enumeration elements list.
FLASHFULL : Key Storage at Flash Full Status Bit (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Key Storage at Flash is not full
#1 : 1
Key Storage at Flash is full
End of enumeration elements list.
INITDONE : Key Store Initialization Done Status (Read Only)
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Key Store is un-initialized
#1 : 1
Key Store is initialized
End of enumeration elements list.
RAMINV : Key Store SRAM Invert Status (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Key Store key in SRAM is normal
#1 : 1
Key Store key in SRAM is inverted
End of enumeration elements list.
Key Store Remaining Space Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RRMNG : Key Store SRAM Remaining Space
The RRMNG shows the remaining byte count space for SRAM.
bits : 0 - 12 (13 bit)
access : read-only
FRMNG : Key Store Flash Remaining Space
The FRMNG shows the remaining byte count space for Flash.
bits : 16 - 27 (12 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.