TAMPER_INIT (INIT)

TAMPER_INTSTS (INTSTS)

TAMPER_LIRCTL (LIRCTL)

TAMPER_TIOCTL (TIOCTL)

TAMPER_SEED (SEED)

TAMPER_SEED2 (SEED2)

TAMPER_ACTSTIOCTL1 (ACTSTIOCTL1)

TAMPER_ACTSTIOCTL2 (ACTSTIOCTL2)

TAMPER_CDBR (CDBR)

TAMPER_VG (VG)

TAMPER_VGEV (VGEV)

TAMPER_LDOTRIM (LDOTRIM)

TAMPER_LBSTRIM (LBSTRIM)

TAMPER_FUNEN (FUNEN)

TAMPER_VG2 (VG2)

TAMPER_TRIEN (TRIEN)

TAMPER_INTEN (INTEN)

TCORERST : Tamper Core Reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TLDORDY : Voltage Regulator Power Ready (Read Only)
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TAMP0IF : Tamper 0 Event Interrupt Flag Note: Write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1IF : Tamper 1 Event Interrupt Flag Note: Write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2IF : Tamper 2 Event Interrupt Flag Note: Write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3IF : Tamper 3 Event Interrupt Flag Note: Write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4IF : Tamper 4 Event Interrupt Flag Note: Write 1 to clear this bit.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5IF : Tamper 5 Event Interrupt Flag Note: Write 1 to clear this bit.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKFAILIF : LXT Clock Frequency Monitor Fail Event Interrupt Flag Note 1: Write 1 to clear this bit to 0. Note 2: LXT detector will be automatically disabled when Fail/Stop flag rises, and resumes after Fail/Stop flag is cleared.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSTOPIF : LXT Clock Frequency Monitor Stop Event Interrupt Flag Note 1: Write 1 to clear this bit to 0. Note 2: LXT detector will be automatically disabled when Fail/Stop flag rises, and resumes after Fail/Stop flag is cleared.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVPOUTIF : VDD Over Voltage Event Interrupt Flag Note: Write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VGPEVIF : Voltage Glitch Positive Detection Interrupt Flag Note: It can be written 1 to clear only (No clear by TCORERST)
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VGNEVIF : Voltage Glitch Negative Detection Interrupt Flag Note: It can be written 1 to clear only (No clear by TCORERST)
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTSEIF : Active Shield Event Detection Interrupt Flag Note: Write 1 to clear this bit after all of ACTSTxIF bits have been cleaned.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTST5IF : Active Shield Tamper 5 Event Interrupt Flag Note: Write 1 to clear this bit.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTST25IF : Active Shield Tamper 5 Event Interrupt Flag Note: Write 1 to clear this bit.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCLVRIF : RTC Low Voltage Detection Event Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIOTRIGIF : RTC Tamper I/O Event Interrupt Flag
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RCLKTRIGIF : RTC Clock Monitor Detection Event Interrupt Flag
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODIF : BOD Event Interrupt Flag Note: It is used to detect the LDO_CAP. Write 1 to clear this bit.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTST1IF : Active Shield Tamper 1 Event Interrupt Flag Note: Write 1 to clear this bit.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTST3IF : Active Shield Tamper 3 Event Interrupt Flag Note: Write 1 to clear this bit.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTST21IF : 2th Active Shield Tamper 1 Event Interrupt Flag Note: Write 1 to clear this bit.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTST23IF : 2th Active Shield Tamper 3 Event Interrupt Flag Note: Write 1 to clear this bit.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TLRCTRIM : Tamper TLIRC32K Trim Value TLIRC32K trim value setting
bits : 0 - 8 (9 bit)
access : read-write

TRIMMOS : Tamper TLIRC32K Trim MOS Value TLIRC32K trim MOS value setting
bits : 9 - 10 (2 bit)
access : read-write

DYN1ISS : Dynamic Pair 1 Input Source Select This bit determines Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. Note: This bit is effective only when DYNPR1EN (TAMPER_TIOCTL[23]) and DYNPR0EN (TAMPER_TIOCTL[15]) are set.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYN2ISS : Dynamic Pair 2 Input Source Select This bit determines Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. Note: This bit has effect only when DYNPR2EN (TAMPER_TIOCTL[31]) and DYNPR0EN (TAMPER_TIOCTL[15]) are set.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNSRC : Dynamic Reference Pattern This field determines the new reference pattern when current pattern run out in dynamic pair mode. Note: After this bit is modified, the SEEDRLD (TAMPER_TIOCTL[4]) should be set.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEEDRLD : Reload New Seed for PRNG Engine Setting this bit, the tamper configuration will be reloaded. Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. Note 2: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNRATE : Dynamic Change Rate This item is choice the dynamic tamper output change rate. Note: After revising this field, setting SEEDRLD (TAMPER_TIOCTL[4]) can reload change rate immediately.
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0EN : Tamper0 Detect Enable Bit Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0LV : Tamper 0 Level This bit depends on level attribute of tamper pin for static tamper detection.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0DBEN : Tamper 0 De-bounce Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1EN : Tamper 1 Detect Enable Bit Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1LV : Tamper 1 Level This bit depends on level attribute of tamper pin for static tamper detection.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1DBEN : Tamper 1 De-bounce Enable Bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNPR0EN : Dynamic Pair 0 Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2EN : Tamper 2 Detect Enable Bit Note: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2LV : Tamper 2 Level This bit depends on level attribute of tamper pin for static tamper detection.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2DBEN : Tamper 2 De-bounce Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3EN : Tamper 3 Detect Enable Bit Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3LV : Tamper 3 Level This bit depends on level attribute of tamper pin for static tamper detection.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3DBEN : Tamper 3 De-bounce Enable Bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNPR1EN : Dynamic Pair 1 Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4EN : Tamper4 Detect Enable Bit Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4LV : Tamper 4 Level This bit depends on level attribute of tamper pin for static tamper detection.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4DBEN : Tamper 4 De-bounce Enable Bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5EN : Tamper 5 Detect Enable Bit Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5LV : Tamper 5 Level This bit depends on level attribute of tamper pin for static tamper detection.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5DBEN : Tamper 5 De-bounce Enable Bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNPR2EN : Dynamic Pair 2 Enable Bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEED : Seed value.
bits : 0 - 31 (32 bit)
access : read-write

SEED2 : Seed value. These seed value are used for 2nd active shield I/O.
bits : 0 - 31 (32 bit)
access : read-write

ADYN1ISS : Active Shied Dynamic Pair 1 Input Source Select This bit determines Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. Note: This bit is effective only when ADYNPR1EN (TAMPER_ACTSTIOCTL1[23]) and ADYNPR0EN (TAMPER_ACTSTIOCTL1[15]) are set.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADYNSRC : Active Shied Dynamic Reference Pattern This field determines the new reference pattern when current pattern run out in dynamic pair mode. Note: After this bit is modified, the SEEDRLD (TAMPER_TIOCTL[4]) should be set.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADYNRATE : Active Shied Dynamic Change Rate Use the bits to choose the dynamic tamper output change rate. Note: After this field is modified, setting SEEDRLD (TAMPER_TIOCTL[4]) can reload the change rate immediately.
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATAMP0EN : Active Shied Tamper0 Detect Enable Bit Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATAMP1EN : Active Shied Tamper 1 Detect Enable Bit Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADYNPR0EN : Active Shied Dynamic Pair 0 Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATAMP2EN : Active Shied Tamper 2 Detect Enable Bit Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATAMP3EN : Active Shied Tamper 3 Detect Enable Bit Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADYNPR1EN : Active Shied Dynamic Pair 1 Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATAMP4EN : Active Tamper4 Detect Enable Bit Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATAMP5EN : Active Tamper 5 Detect Enable Bit Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADYNPR2EN : Active Shied Dynamic Pair 2 Enable Bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADYN1ISS2 : Active Shied Dynamic Pair 1 Input Source Select 2 This bit determines if Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. Note: This bit is effective only when ADYNPR1EN2 (TAMPER_ACTSTIOCTL2[23]) and ADYNPR0EN2 (TAMPER_ACTSTIOCTL2[15]) are set.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADYNSRC2 : Active Shied Dynamic Reference Pattern 2 This field determines the new reference pattern when current pattern run out in dynamic pair mode. Note: After this bit is modified, the SEEDRLD2 (TAMPER_ACTSTIOCTL2[4]) should be set.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEEDRLD2 : Reload New Seed for PRNG Engine 2 Setting this bit, the tamper configuration will be reloaded. Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. Note 2: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADYNRATE2 : Active Shied Dynamic Change Rate 2 Use the bits to choose the dynamic tamper output change rate. Note: After this field is modified, setting SEEDRLD2 (TAMPER_ACTSTIOCTL2[4]) can reload change rate immediately.
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATAMP0EN2 : Active Shied Tamper0 Detect Enable Bit 2 Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATAMP1EN2 : Active Shied Tamper 1 Detect Enable Bit 2 Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADYNPR0EN2 : Active Shied Dynamic Pair 0 Enable Bit 2
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATAMP2EN2 : Active Shied Tamper 2 Detect Enable Bit 2 Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATAMP3EN2 : Active Shied Tamper 3 Detect Enable Bit 2 Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADYNPR1EN2 : Active Shied Dynamic Pair 1 Enable Bit 2
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATAMP4EN2 : Active Shied Tamper4 Detect Enable Bit 2 Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATAMP5EN2 : Active Tamper 5 Detect Enable Bit 2 Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADYNPR2EN2 : Active Shied Dynamic Pair 2 Enable Bit 2
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOPBD : LXT Clock Frequency Detector Stop Boundary The bits define the stop value of frequency monitor window. When LXT frequency monitor counter lower than Clock Frequency Detector Stop Boundary, the LXT frequency detect stop interrupt flag will set to 1. Note: The boundary is defined as the maximum value of LXT among 256 Tamper clock time.
bits : 0 - 7 (8 bit)
access : read-write

FAILBD : LXT Clock Frequency Detector Fail Boundary The bits define the fail value of frequency monitor window. When LXT frequency monitor counter lower than Clock Frequency Detector Fail Boundary, the LXT frequency detect fail interrupt flag will set to 1. Note: The boundary is defined as the minimum value of LXT among 256 Tamper clock time.
bits : 16 - 23 (8 bit)
access : read-write

PCLKSEL0 : PL0 Positive Clock Trim Range The setting value of the positive clock tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%. Note: PL0 means the power level is 1.26V The power level is controlled in system manager
bits : 0 - 3 (4 bit)
access : read-write

NCLKSEL0 : PL0 Negative Clock Trim Range The setting value of the negative clock tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%.
bits : 4 - 7 (4 bit)
access : read-write

PDATSEL0 : PL0 Positive Data Trim Range The setting value of the positive data tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%.
bits : 8 - 11 (4 bit)
access : read-write

NDATSEL0 : PL0 Negative Data Trim Range The setting value of the negative data tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%.
bits : 12 - 15 (4 bit)
access : read-write

PCLKSEL1 : PL1 Positive Clock Trim Range The setting value of the positive clock tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%. Note: PL1 means the power level is 1.2V
bits : 16 - 19 (4 bit)
access : read-write

NCLKSEL1 : PL1 Negative Clock Trim Range The setting value of the negative clock tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%.
bits : 20 - 23 (4 bit)
access : read-write

PDATSEL1 : PL1 Positive Data Trim Range The setting value of the positive data tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%.
bits : 24 - 27 (4 bit)
access : read-write

NDATSEL1 : PL1 Negative Data Trim Range The setting value of the negative data tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%.
bits : 28 - 31 (4 bit)
access : read-write

VGECNTP : Positive Voltage Glitch Error Tolerance The value indicates the tolerance count for positive voltage glitch event.
bits : 0 - 7 (8 bit)
access : read-write

VGECNTN : Negative Voltage Glitch Error Tolerance The value indicates the tolerance count for negative voltage glitch event.
bits : 8 - 15 (8 bit)
access : read-write

TLDOTRIM : Voltage Regulator Output Voltage Trim The value indicates the trim value of the voltage regulator output voltage.
bits : 0 - 3 (4 bit)
access : read-write

TLDOIQSEL : Voltage Regulator Qu Current Selection Indicates the Qu current selection of voltage regulator.
bits : 8 - 9 (2 bit)
access : read-write

TLVDSEL : Under-shoot Detect Level Trim Bits The value indicates the trim value of the under-shoot detection level
bits : 0 - 2 (3 bit)
access : read-write

TOVDSEL : Over-shoot Detect Level Trim Bits The value indicates the trim value of the over-shoot detection level
bits : 4 - 4 (1 bit)
access : read-write

BSCMPLV : Under-shoot Detect Comparator Current Trim Bits The value indicates the trim value of the under-shoot detection comparator current trim level
bits : 8 - 9 (2 bit)
access : read-write

BSCMPOV : Over-shoot Detect Comparator Current Trim Bits The value indicates the trim value of the over-shoot detection comparator current trim level
bits : 10 - 11 (2 bit)
access : read-write

HYSCMPLV : Under-shoot Detect Comparator Hysteresis Trim Bits The value indicates the trim value of the under-shoot detection comparator of hysteresis trim level
bits : 12 - 13 (2 bit)
access : read-write

HYSCMPOV : Over-shoot Detect Comparator Hysteresis Trim Bits The value indicates the trim value of the over-shoot detection comparator of hysteresis trim level
bits : 14 - 15 (2 bit)
access : read-write

LXTDETEN : LXT Clock Detection Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMPIOSEL : Tamper I/O Detection Selection Bit
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRC48MEN : HIRC48M Enable Bit The HIRC48M is disabled when these bits equal 0x5A, otherwise it will be enabled with any other values.
bits : 16 - 23 (8 bit)
access : read-write

VGCHEN0 : Voltage Glitch Channel 0 Enable Bit Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VGCHEN1 : Voltage Glitch Channel 1 Enable Bit Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VGCHEN2 : Voltage Glitch Channel 2 Enable Bit Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VGCHEN3 : Voltage Glitch Channel 3 Enable Bit Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PCLKSEL2 : PL2 Positive Clock Trim Range The setting value of the positive clock tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%. Note: PL2 means the power level is 1.1V The power level is controlled in system manager.
bits : 0 - 3 (4 bit)
access : read-write

NCLKSEL2 : PL2 Negative Clock Trim Range The setting value of the negative clock tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%.
bits : 4 - 7 (4 bit)
access : read-write

PDATSEL2 : PL2 Positive Data Trim Range The setting value of the positive data tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%.
bits : 8 - 11 (4 bit)
access : read-write

NDATSEL2 : PL2 Negative Data Trim Range The setting value of the negative data tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%.
bits : 12 - 15 (4 bit)
access : read-write

PCLKSEL3 : PL3 Positive Clock Trim Range The setting value of the positive clock tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%. Note: PL3 means the power level is 0.9V
bits : 16 - 19 (4 bit)
access : read-write

NCLKSEL3 : PL3 Negative Clock Trim Range The setting value of the negative clock tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%.
bits : 20 - 23 (4 bit)
access : read-write

PDATSEL3 : PL3 Positive Data Trim Range The setting value of the positive data tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%.
bits : 24 - 27 (4 bit)
access : read-write

NDATSEL3 : PL3 Negative Data Trim Range The setting value of the negative data tolerance. One step is about 2.5% tolerance. The maximum tolerance is 20%.
bits : 28 - 31 (4 bit)
access : read-write

KSTRIGEN : Key Store Trigger Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKEUPEN : Wakeup Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRYPTOEN : Crypto Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHIPRSTEN : Chip Reset Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCSPCLREN : RTC Spare Register Clear Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0IEN : Tamper 0 Event Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1IEN : Tamper 1 or Pair 0 Event Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2IEN : Tamper 2 Event Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3IEN : Tamper 3 or Pair 1 Event Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4IEN : Tamper 4 Event Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5IEN : Tamper 5 or Pair 2 Event Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKFIEN : LXT Clock Frequency Monitor Fail Event Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSTOPIEN : LXT Clock Frequency Monitor Stop Event Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVPIEN : VDD Over Voltage Protect Detection Interrupt Enable Bit Note: The function enable of the over voltage detection is defined in system manager.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VGPIEN : Voltage Glitch Positive Detection Event Interrupt Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VGNIEN : Voltage Glitch Negative Detection Event Interrupt Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTSIEN : Active Shield Event Interrupt Enable Bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCLVRIEN : RTC Low Voltage Detection Event Interrupt Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCIOIEN : RTC Tamper I/O Event Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCLKIEN : RTC Clock Monitor Detection Event Interrupt Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODIEN : BOD Event Interrupt Enable Bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.