ECAP_CNT

ECAP_CNTCMP

ECAP_CTL0

ECAP_CTL1

ECAP_STATUS

ECAP_HLD0

ECAP_HLD1

ECAP_HLD2

CNT : Input Capture Timer/Counter The input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider.
bits : 0 - 23 (24 bit)
access : read-write

CNTCMP : Input Capture Counter Compare Register
bits : 0 - 23 (24 bit)
access : read-write

NFCLKSEL : Noise Filter Clock Pre-divide Selection To determine the sampling frequency of the Noise Filter clock
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPNFDIS : Input Capture Noise Filter Disable Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC0EN : Port Pin IC0 Input to Input Capture Unit Enable Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC1EN : Port Pin IC1 Input to Input Capture Unit Enable Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC2EN : Port Pin IC2 Input to Input Capture Unit Enable Control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPSEL0 : CAP0 Input Source Selection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPSEL1 : CAP1 Input Source Selection
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPSEL2 : CAP2 Input Source Selection
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIEN0 : Input Capture Channel 0 Interrupt Enable Control
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIEN1 : Input Capture Channel 1 Interrupt Enable Control
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIEN2 : Input Capture Channel 2 Interrupt Enable Control
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVIEN : CAPOVF Trigger Input Capture Interrupt Enable Bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPIEN : CAPCMPF Trigger Input Capture Interrupt Enable Bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN : Input Capture Counter Start Counting Control Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting the clock.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCLREN : Input Capture Counter Cleared by Compare-match Control
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPEN : Compare Function Enable Bit The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEN : Input Capture Timer/Counter Enable Bit
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EDGESEL0 : Channel 0 Captured Edge Selection Input capture0 can detect falling edge change only, rising edge change only or both edge change
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EDGESEL1 : Channel 1 Captured Edge Selection Input capture1 can detect falling edge change only, rising edge change only or both edge change
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EDGESEL2 : Channel 2 Captured Edge Selection Input capture2 can detect falling edge change only, rising edge change only or both edge changes
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAP0RLDEN : Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAP1RLDEN : Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAP2RLDEN : Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVRLDEN : Capture Counter's Reload Function Triggered by Overflow Enable Bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSEL : Capture Timer Clock Divide Selection The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTSRCSEL : Capture Timer/Counter Clock Source Selection Select the capture timer/counter clock source.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAP0CLREN : Capture Counter Cleared by Capture Event0 Control
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAP1CLREN : Capture Counter Cleared by Capture Event1 Control
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAP2CLREN : Capture Counter Cleared by Capture Event2 Control
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF0 : Input Capture Channel 0 Triggered Flag When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. Note: This bit is only cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF1 : Input Capture Channel 1 Triggered Flag When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. Note: This bit is only cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF2 : Input Capture Channel 2 Triggered Flag When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. Note: This bit is only cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCMPF : Input Capture Compare-match Flag If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value. Note: This bit is only cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPOVF : Input Capture Counter Overflow Flag Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero. Note: This bit is only cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAP0 : Value of Input Channel 0, CAP0 (Read Only) Reflecting the value of input channel 0, CAP0 Note: The bit is read only and write is ignored.
bits : 8 - 8 (1 bit)
access : read-only

CAP1 : Value of Input Channel 1, CAP1 (Read Only) Reflecting the value of input channel 1, CAP1 Note: The bit is read only and write is ignored.
bits : 9 - 9 (1 bit)
access : read-only

CAP2 : Value of Input Channel 2, CAP2 (Read Only) Reflecting the value of input channel 2, CAP2. Note: The bit is read only and write is ignored.
bits : 10 - 10 (1 bit)
access : read-only

HOLD : Input Capture Counter Hold Register When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
bits : 0 - 23 (24 bit)
access : read-write