SDH_DMACTL

SDH_DMASA

SDH_DMABCNT

SDH_DMAINTEN

SDH_DMAINTSTS

SDH_GCTL

SDH_GINTEN

SDH_GINTSTS

SDH_CTL

SDH_CMDARG

SDH_INTEN

SDH_INTSTS

SDH_RESP0

SDH_RESP1

SDH_BLEN

SDH_TOUT

DMAEN : DMA Engine Enable Bit Note 1: If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. Note 2: If target abort occurred, DMAEN will be cleared.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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DMARST : Software Engine Reset Note: The software reset DMA related registers.
bits : 1 - 1 (1 bit)
access : read-write

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SGEN : Scatter-gather Function Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

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DMABUSY : DMA Transfer Is in Progress This bit indicates if SD Host is granted and doing DMA transfer or not.
bits : 9 - 9 (1 bit)
access : read-write

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ORDER : Determined to the PAD Table Fetching Is in Order or Out of Order
bits : 0 - 0 (1 bit)
access : read-write

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DMASA : DMA Transfer Starting Address This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data. If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table. Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004.
bits : 1 - 31 (31 bit)
access : read-write

BCNT : DMA Transfer Byte Count (Read Only) This field indicates the remained byte count of DMA transfer. The value of this field is valid only when DMA is busy otherwise, it is 0.
bits : 0 - 25 (26 bit)
access : read-only

ABORTIEN : DMA Read/Write Target Abort Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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WEOTIEN : Wrong EOT Encountered Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

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ABORTIF : DMA Read/Write Target Abort Interrupt Flag (Read Only) Note 1: This bit is read only, but can be cleared by writing '1' to it. Note 2: When DMA's bus master received ERROR response, it means that target abort happened. DMA will stop transfer and respond this event and then go to IDLE state. When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again.
bits : 0 - 0 (1 bit)
access : read-only

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WEOTIF : Wrong EOT Encountered Interrupt Flag (Read Only) When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set. Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-only

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GCTLRST : Software Engine Reset
bits : 0 - 0 (1 bit)
access : read-write

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SDEN : Secure Digital Functionality Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

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DTAIEN : DMA READ/WRITE Target Abort Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

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DTAIF : DMA READ/WRITE Target Abort Interrupt Flag (Read Only) This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation. When Target Abort is occurred, please reset all engine. Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-only

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COEN : Command Output Enable Bit Note: When operation is finished, this bit will be cleared automatically, so do not write 0 to this bit (the controller will be abnormal).
bits : 0 - 0 (1 bit)
access : read-write

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RIEN : Response Input Enable Bit Note: When operation is finished, this bit will be cleared automatically, so do not write 0 to this bit (the controller will be abnormal).
bits : 1 - 1 (1 bit)
access : read-write

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DIEN : Data Input Enable Bit Note: When operation is finished, this bit will be cleared automatically, so do not write 0 to this bit (the controller will be abnormal).
bits : 2 - 2 (1 bit)
access : read-write

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DOEN : Data Output Enable Bit Note: When operation is finished, this bit will be cleared automatically, so do not write 0 to this bit (the controller will be abnormal).
bits : 3 - 3 (1 bit)
access : read-write

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R2EN : Response R2 Input Enable Bit Note: When operation is finished, this bit will be cleared automatically, so do not write 0 to this bit (the controller will be abnormal).
bits : 4 - 4 (1 bit)
access : read-write

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CLK74OEN : Initial 74 Clock Cycles Output Enable Bit Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
bits : 5 - 5 (1 bit)
access : read-write

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CLK8OEN : Generating 8 Clock Cycles Output Enable Bit Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
bits : 6 - 6 (1 bit)
access : read-write

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CLKKEEP : SD Clock Enable Control
bits : 7 - 7 (1 bit)
access : read-write

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CMDCODE : SD Command Code The bits contain the SD command code (0x00 - 0x3F).
bits : 8 - 13 (6 bit)
access : read-write

CTLRST : Software Engine Reset
bits : 14 - 14 (1 bit)
access : read-write

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DBW : SD Data Bus Width (for 1-bit / 4-bit Selection)
bits : 15 - 15 (1 bit)
access : read-write

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BLKCNT : Block Counts to Be Transferred or Received This field contains the block counts for data-in and data-out transfer. For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance. Do not fill 0x0 to this field. Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
bits : 16 - 23 (8 bit)
access : read-write

SDNWR : NWR Parameter for Block Write Operation This value indicates the NWR parameter for data block write operation in SD clock counts. The actual clock cycle will be SDNWR+1.
bits : 24 - 27 (4 bit)
access : read-write

ARGUMENT : SD Command Argument This register contains a 32-bit value specifies the argument of SD command from host controller to SD card. Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
bits : 0 - 31 (32 bit)
access : read-write

BLKDIEN : Block Transfer Done Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

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CRCIEN : CRC7, CRC16 and CRC Status Error Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

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CDIEN : SD Card Detection Interrupt Enable Bit Enable/Disable interrupts generation of SD controller when card is inserted or removed.
bits : 8 - 8 (1 bit)
access : read-write

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RTOIEN : Response Time-out Interrupt Enable Bit Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out. Time-out value is specified at TOUT register.
bits : 12 - 12 (1 bit)
access : read-write

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DITOIEN : Data Input Time-out Interrupt Enable Bit Enable/Disable interrupts generation of SD controller when data input time-out. Time-out value is specified at TOUT register.
bits : 13 - 13 (1 bit)
access : read-write

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WKIEN : Wake-up Signal Generating Enable Bit Enable/Disable wake-up signal generating of SD controller when card is inserted or removed.
bits : 14 - 14 (1 bit)
access : read-write

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CDSRC : SD Card Detect Source Selection
bits : 30 - 30 (1 bit)
access : read-write

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BLKDIF : Block Transfer Done Interrupt Flag (Read Only) This bit indicates that SD host has finished all data-in or data-out block transfer. If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set. Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-only

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CRCIF : CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer. When CRC error is occurred, software should reset SD engine. Some response (ex. R3) doesn't have CRC7 information with it SD host will still calculate CRC7, get CRC error and set this flag. In this condition, software should ignore CRC error and clears this bit manually. Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-only

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CRC7 : CRC7 Check Status (Read Only) SD host will check CRC7 correctness during each response in. If that response does not contain CRC7 information (ex. R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.
bits : 2 - 2 (1 bit)
access : read-only

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CRC16 : CRC16 Check Status of Data-in Transfer (Read Only) SD host will check CRC16 correctness after data-in transfer.
bits : 3 - 3 (1 bit)
access : read-only

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CRCSTS : CRC Status Value of Data-out Transfer (Read Only) SD host will record CRC status of data-out transfer. Software could use this value to identify what type of error is during data-out transfer.
bits : 4 - 6 (3 bit)
access : read-only

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DAT0STS : DAT0 Pin Status of Current Selected SD Port (Read Only) This bit is the DAT0 pin status of current selected SD port.
bits : 7 - 7 (1 bit)
access : read-only

CDIF : SD Card Detection Interrupt Flag (Read Only) This bit indicates that SD card is inserted or removed. Only when CDIEN (SDH_INTEN[8]) is set to 1, this bit is active. Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 8 - 8 (1 bit)
access : read-only

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RTOIF : Response Time-out Interrupt Flag (Read Only) This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit). Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 12 - 12 (1 bit)
access : read-only

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DITOIF : Data Input Time-out Interrupt Flag (Read Only) This bit indicates that SD host counts to time-out value when receiving data (waiting start bit). Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 13 - 13 (1 bit)
access : read-only

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CDSTS : Card Detect Status of SD (Read Only) This bit indicates the card detect pin status of SD, and is used for card detection. When there is a card inserted in or removed from SD, software should check this bit to confirm if there is really a card insertion or removal.
bits : 16 - 16 (1 bit)
access : read-only

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DAT1STS : DAT1 Pin Status of SD Card (Read Only) This bit indicates the DAT1 pin status of SD card.
bits : 18 - 18 (1 bit)
access : read-only

RESPTK0 : SD Receiving Response Token 0 (Read Only) SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This field contains response bit 47-16 of the response token.
bits : 0 - 31 (32 bit)
access : read-only

RESPTK1 : SD Receiving Response Token 1 (Read Only) The SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This register contains the bit 15-8 of the response token.
bits : 0 - 7 (8 bit)
access : read-only

BLKLEN : SD BLOCK LENGTH in Byte Unit A 11-bit value specifies the SD transfer byte count of a block. The actual byte count is equal to BLKLEN+1. Note: The default SD block length is 512 bytes.
bits : 0 - 10 (11 bit)
access : read-write

TOUT : SD Response/Data-in Time-out Value A 24-bit value specifies the time-out counts of response and data input. SD host controller will wait start bit of response or data-in until this value reached. The time period depends on SD engine clock frequency. Do not write a small number into this field, or you may never get response or data due to time-out. Note: Filling 0x0 into this field will disable hardware time-out function.
bits : 0 - 23 (24 bit)
access : read-write