CRYPTO_AES_FDBCK0

CRYPTO_AES_GCM_IVCNT0

CRYPTO_AES_GCM_IVCNT1

CRYPTO_AES_GCM_ACNT0

CRYPTO_AES_GCM_ACNT1

CRYPTO_AES_FDBCK1

CRYPTO_AES_GCM_PCNT0

CRYPTO_AES_GCM_PCNT1

CRYPTO_AES_FBADDR

CRYPTO_AES_FDBCK2

CRYPTO_AES_CTL

CRYPTO_AES_STS

CRYPTO_AES_DATIN

CRYPTO_AES_DATOUT

CRYPTO_AES_FDBCK3

CRYPTO_AES_KEY0

CRYPTO_AES_KEY1

CRYPTO_AES_KEY2

CRYPTO_AES_KEY3

CRYPTO_AES_KEY4

CRYPTO_AES_KEY5

CRYPTO_AES_KEY6

CRYPTO_AES_KEY7

CRYPTO_AES_IV0

CRYPTO_AES_IV1

CRYPTO_AES_IV2

CRYPTO_AES_IV3

CRYPTO_AES_KSCTL

CRYPTO_AES_SADDR

CRYPTO_AES_DADDR

CRYPTO_AES_CNT

FDBCK : AES Feedback Information The feedback value is 128 bits in size. The AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode. The AES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to CRYPTO_AES_IVx in the same channel operation, and then continue the operation with the original setting.
bits : 0 - 31 (32 bit)
access : read-only

CNT : AES GCM IV Byte Count The bit length of IV is 64 bits for AES GCM mode. The CRYPTO_AES_GCM_IVCNT0 keeps the low weight byte count of initial vector (i.e., len(IV)[34:3]) of AES GCM mode and can be read and written.
bits : 0 - 31 (32 bit)
access : read-write

CNT : AES GCM IV Byte Count The bit length of IV is 64 bits for AES GCM mode. The CRYPTO_AES_GCM_IVCNT1 keeps the high weight byte count of initial vector (i.e., len(IV)[64:35]) of AES GCM mode and can be read and written.
bits : 0 - 28 (29 bit)
access : read-write

CNT : AES GCM a Byte Count The bit length of A is 64 bits for AES GCM mode. The CRYPTO_AES_GCM_ACNT0 keeps the low weight byte count of the additional authenticated data (i.e., len(A)[34:3]) of AES GCM mode and can be read and written.
bits : 0 - 31 (32 bit)
access : read-write

CNT : AES GCM a Byte Count The bit length of A is 64 bits for AES GCM mode. The CRYPTO_AES_GCM_ACNT0 keeps the high weight byte count of the additional authenticated data (i.e., len(A)[63:35]) of AES GCM mode and can be read and written.
bits : 0 - 28 (29 bit)
access : read-write

CNT : AES GCM P Byte Count The bit length of Por C is 39 bits for AES GCM mode. The CRYPTO_AES_GCM_PCNT0 keeps the low weight byte count of the plaintext or ciphertext (i.e., len(P)[34:3] or len(C)[34:3]) of AES GCM mode and can be read and written.
bits : 0 - 31 (32 bit)
access : read-write

CNT : AES GCM P Byte Count The bit length of Por C is 39 bits for AES GCM mode. The CRYPTO_AES_GCM_PCNT1 keeps the high weight byte count of the plaintext or ciphertext (i.e., len(P)[38:35] or len(C)[38:35]) of AES GCM mode and can be read and written. The bit length of Por C is 64 bits for AES CCM mode. The CRYPTO_AES_GCM_PCNT1 keeps the high weight byte count of the plaintext or ciphertext (i.e., len(P)[63:35] or len(C)[63:35]) of AES CCM mode and can be read and written.
bits : 0 - 28 (29 bit)
access : read-write

FBADDR : AES DMA Feedback Address In DMA cascade mode, software can update DMA feedback address register for automatically reading and writing feedback values via DMA.The FBADDR keeps the feedback address of the feedback data for the next cascade operation. Based on the feedback address, the AES accelerator can read thefeedback data of the last cascade opeation from SRAM memory space and write thefeedback data of the current cascade opeation to SRAM memory space. The start of feedback address should be located at word boundary. In other words, bit 1 and 0 of FBADDR are ignored. FBADDR can be read and written. In DMA mode, software can update the next CRYPTO_AES_FBADDR before triggering START.
bits : 0 - 31 (32 bit)
access : read-write

START : AES Engine Start Note: This bit is always 0 when it is read back.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP : AES Engine Stop Note: This bit is always 0 when it is read back.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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KEYSZ : AES Key Size This bit defines three different key size for AES operation.
bits : 2 - 3 (2 bit)
access : read-write

DMALAST : AES Last Block In DMA mode, this bit must be set as beginning the last DMA cascade round. In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. This bit is always 0 when it is read back. Must be written again once START is triggered.
bits : 5 - 5 (1 bit)
access : read-write

DMACSCAD : AES Engine DMA with Cascade Mode
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

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DMAEN : AES Engine DMA Enable Bit The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

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OPMODE : AES Engine Operation Modes
bits : 8 - 15 (8 bit)
access : read-write

Enumeration:

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ENCRYPTO : AES Encryption/Decryption
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

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SM4EN : SM4 Engine Enable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

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FBIN : Feedback Input to AES Via DMA Automatically
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

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FBOUT : Feedback Output From AES Via DMA Automatically
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

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OUTSWAP : AES Engine Output Data Swap
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

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INSWAP : AES Engine Input Data Swap
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

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KOUTSWAP : AES Engine Output Key, Initial Vector and Feedback Swap
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

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KINSWAP : AES Engine Input Key and Initial Vector Swap
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

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KEYUNPRT : Unprotect Key Writing 0 to CRYPTO_AES_CTL[31] and '10110' to CRYPTO_AES_CTL[30:26] is to unprotect the AES key. The KEYUNPRT can be read and written. When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
bits : 26 - 30 (5 bit)
access : read-write

KEYPRT : Protect Key Read as a flag to reflect KEYPRT.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

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BUSY : AES Engine Busy
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

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INBUFEMPTY : AES Input Buffer Empty
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

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INBUFFULL : AES Input Buffer Full Flag
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

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INBUFERR : AES Input Buffer Error Flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

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CNTERR : CRYPTO_AES_CNT Setting Error
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

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OUTBUFEMPTY : AES Out Buffer Empty
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OUTBUFFULL : AES Out Buffer Full Flag
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OUTBUFERR : AES Out Buffer Error Flag
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUSERR : AES DMA Access Bus Error Flag
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

KSERR : AES Engine Access Key Store Error Flag
bits : 21 - 21 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DATIN : AES Engine Input Port CPU feeds data to AES engine through this port by checking CRYPTO_AES_STS. Feed data as INBUFFULL is 0.
bits : 0 - 31 (32 bit)
access : read-write

DATOUT : AES Engine Output Port CPU gets results from the AES engine through this port by checking CRYPTO_AES_STS. Get data as OUTBUFEMPTY is 0.
bits : 0 - 31 (32 bit)
access : read-only

KEY : CRYPTO_AES_KEYx The KEY keeps the security key for AES operation. The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. {CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 128-bit security key for AES operation. {CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 192-bit security key for AES operation. {CRYPTO_AES_KEY7, CRYPTO_AES_KEY6, CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 256-bit security key for AES operation.
bits : 0 - 31 (32 bit)
access : read-write

IV : AES Initial Vectors Four initial vectors (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) are for AES operating in CBC, CFB, and OFB mode. Four registers (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
bits : 0 - 31 (32 bit)
access : read-write

NUM : Read Key Number The key number is sent to key store
bits : 0 - 4 (5 bit)
access : write-only

RSRC : Read Key Source
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

RSSRC : Read Key Store Source
bits : 6 - 7 (2 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SADDR : AES DMA Source Address The AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of SADDR are ignored. SADDR can be read and written. Writing to SADDR while the AES accelerator is operating does not affect the current AES operation. But the value of SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next AES operation. In DMA mode, software can update the next CRYPTO_AES_SADDR before triggering START. The value of CRYPTO_AES_SADDR and CRYPTO_AES_DADDR can be the same.
bits : 0 - 31 (32 bit)
access : read-write

DADDR : AES DMA Destination Address The AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO. The DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of DADDR are ignored. DADDR can be read and written. Writing to DADDR while the AES accelerator is operating does not affect the current AES operation. But the value of DADDR will be updated later on. Consequently, software can prepare the destination address for the next AES operation. In DMA mode, software can update the next CRYPTO_AES_DADDR before triggering START. The value of CRYPTO_AES_SADDR and CRYPTO_AES_DADDR can be the same.
bits : 0 - 31 (32 bit)
access : read-write

CNT : AES Byte Count The CRYPTO_AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. The CRYPTO_AES_CNT is 32-bit and the maximum of byte count is 4G bytes. CRYPTO_AES_CNT can be read and written. Writing to CRYPTO_AES_CNT while the AES accelerator is operating does not affect the current AES operation. But the value of CRYPTO_AES_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next AES operation. According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes. Operations that are qual or less than one block will output unexpected result. In Non-DMA ECB, CBC, CFB, OFB, CTR, CCM and GCM mode, CRYPTO_AES_CNT must be set as byte count for the last block of data before feeding in the last block of data. In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRYPTO_AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. In AES GCM mode without DMA cascade function, the value of CRYPTO_AES_CNT is equal to the total value of {CRYPTO_AES_GCM_IVCNT1, CRYPTO_AES_GCM_IVCNT0}, {CRYPTO_AES_GCM_ACNT1, CRYPTO_AES_GCM_ACNT0} and {CRYPTO_AES_GCM_PCNT1, CRYPTO_AES_GCM_PCNT0}. In AES GCM mode with DMA cascade function, the value of CRYPTO_AES_CNT represents the byte count of source text in this cascade function. Thus, the value of CRYPTO_AES_CNT is less than or equal to the total value of {CRYPTO_AES_GCM_IVCNT1, CRYPTO_AES_GCM_IVCNT0}, {CRYPTO_AES_GCM_ACNT1, CRYPTO_AES_GCM_ACNT0} and {CRYPTO_AES_GCM_PCNT1, CRYPTO_AES_GCM_PCNT0} and must be block alignment. In AES CCM mode without DMA cascade function, the value of CRYPTO_AES_CNT is equal to the total value of {CRYPTO_AES_GCM_ACNT1, CRYPTO_AES_GCM_ACNT0} and {CRYPTO_AES_GCM_PCNT1, CRYPTO_AES_GCM_PCNT0}. In AES CCM mode with DMA cascade function, the value of CRYPTO_AES_CNT represents the byte count of source text in this cascade function. Thus, the value of CRYPTO_AES_CNT is less than or equal to the total value of {CRYPTO_AES_GCM_ACNT1, CRYPTO_AES_GCM_ACNT0} and {CRYPTO_AES_GCM_PCNT1, CRYPTO_AES_GCM_PCNT0} and must be block alignment, except for the last block of plaintext or ciphertext.
bits : 0 - 31 (32 bit)
access : read-write