Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
Crypto Interrupt Enable Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AESIEN : AES Interrupt Enable Bit
Note: In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.
In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES interrupt Disabled
#1 : 1
AES interrupt Enabled
End of enumeration elements list.
AESEIEN : AES Error Flag Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES error interrupt flag Disabled
#1 : 1
AES error interrupt flag Enabled
End of enumeration elements list.
PRNGIEN : PRNG Interrupt Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PRNG interrupt Disabled
#1 : 1
PRNG interrupt Enabled
End of enumeration elements list.
PRNGEIEN : PRNG Error Flag Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PRNG error interrupt flag Disabled
#1 : 1
PRNG error interrupt flag Enabled
End of enumeration elements list.
ECCIEN : ECC Interrupt Enable Bit
Note: In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine. In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECC interrupt Disabled
#1 : 1
ECC interrupt Enabled
End of enumeration elements list.
ECCEIEN : ECC Error Interrupt Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECC error interrupt flag Disabled
#1 : 1
ECC error interrupt flag Enabled
End of enumeration elements list.
HMACIEN : SHA/HMAC Interrupt Enable Bit
Note: In DMA mode, an interrupt will be triggered when amount of data set in HMAC_DMA_CNT is fed into the SHA/HMAC engine. In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
SHA/HMAC interrupt Disabled
#1 : 1
SHA/HMAC interrupt Enabled
End of enumeration elements list.
HMACEIEN : SHA/HMAC Error Interrupt Enable Bit
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
SHA/HMAC error interrupt flag Disabled
#1 : 1
HMAC error interrupt flag Enabled
End of enumeration elements list.
RSAIEN : RSA Interrupt Enable Bit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
RSA interrupt Disabled
#1 : 1
RSA interrupt Enabled
End of enumeration elements list.
RSAEIEN : RSA Error Interrupt Enable Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
RSA error interrupt flag Disabled
#1 : 1
RSA error interrupt flag Enabled
End of enumeration elements list.
Crypto Interrupt Flag
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AESIF : AES Finish Interrupt Flag
Note: This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AES interrupt
#1 : 1
AES encryption/decryption done interrupt
End of enumeration elements list.
AESEIF : AES Error Flag
Note: This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AES error
#1 : 1
AES encryption/decryption error interrupt
End of enumeration elements list.
PRNGIF : PRNG Finish Interrupt Flag
Note: This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No PRNG interrupt
#1 : 1
PRNG key generation done interrupt
End of enumeration elements list.
PRNGEIF : PRNG Error Flag
Note: This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No PRNG error
#1 : 1
PRNG key generation error interrupt
End of enumeration elements list.
ECCIF : ECC Finish Interrupt Flag
Note: This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ECC interrupt
#1 : 1
ECC operation done interrupt
End of enumeration elements list.
ECCEIF : ECC Error Flag
This register includes operating and setting error. The detail flag is shown in CRYPTO_ECC_STS register.
Note: This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ECC error
#1 : 1
ECC error interrupt
End of enumeration elements list.
HMACIF : SHA/HMAC Finish Interrupt Flag
Note: This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No SHA/HMAC interrupt
#1 : 1
SHA/HMAC operation done interrupt
End of enumeration elements list.
HMACEIF : SHA/HMAC Error Flag
This register includes operating and setting error. The detail flag is shown in CRYPTO_HMAC_STS register.
Note: This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No SHA/HMAC error
#1 : 1
SHA/HMAC error interrupt
End of enumeration elements list.
RSAIF : RSA Finish Interrupt Flag
This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
No RSA interrupt
#1 : 1
RSA operation done interrupt
End of enumeration elements list.
RSAEIF : RSA Error Interrupt Flag
This register includes operating and setting error. The detail flag is shown in CRYPTO_RSA_STS register.
This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No RSA error
#1 : 1
RSA error interrupt
End of enumeration elements list.
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