CRYPTO_RSA_CTL

CRYPTO_RSA_SADDR2

CRYPTO_RSA_SADDR3

CRYPTO_RSA_SADDR4

CRYPTO_RSA_DADDR

CRYPTO_RSA_MADDR0

CRYPTO_RSA_MADDR1

CRYPTO_RSA_MADDR2

CRYPTO_RSA_MADDR3

CRYPTO_RSA_MADDR4

CRYPTO_RSA_MADDR5

CRYPTO_RSA_MADDR6

CRYPTO_RSA_STS

CRYPTO_RSA_KSCTL

CRYPTO_RSA_KSSTS0

CRYPTO_RSA_KSSTS1

CRYPTO_RSA_SADDR0

CRYPTO_RSA_SADDR1

START : RSA Accelerator Start This bit is always 0 when it is read back. RSA accelerator will ignore this START signal when BUSY flag is 1.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP : RSA Accelerator Stop Note: This bit is always 0 when it is read back. Remember to clear RSA interrupt flag after stopping RSA accelerator.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRT : CRT Enable Control Note: CRT is only used in decryption with key length 2048, 3072,4096 bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRTBYP : CRT Bypass Enable Control CRT bypass is only used in CRT decryption with the same key. Note: If users want to decrypt repeatedly with the same key, they can execute CRT bypass mode after the first time CRT decryption (means the second time to the latest time), but they cannot set CRTBYP to 1 in non-CRT mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEYLENG : The Key Length of RSA Operation
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCAP : Side Channel Attack Protection Enable Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SADDR2 : RSA DMA Source Address Register2 The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. This register is stored in the address of RSA the Exponent of Exponentiation (E).
bits : 0 - 31 (32 bit)
access : read-write

SADDR3 : RSA DMA Source Address Register3 The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. This register is stored in the address of RSA the Factor of Modulus Operation (p).
bits : 0 - 31 (32 bit)
access : read-write

SADDR4 : RSA DMA Source Address Register4 The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. This register is stored in the address of RSA the Factor of Modulus Operation (q).
bits : 0 - 31 (32 bit)
access : read-write

DADDR : RSA DMA Destination Address Register The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. This register is stored in the address of RSA DMA Destination Address Register (Ans).
bits : 0 - 31 (32 bit)
access : read-write

MADDR0 : RSA DMA Middle Address Register0 The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator.
bits : 0 - 31 (32 bit)
access : read-write

MADDR1 : RSA DMA Middle Address Register1 The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator.
bits : 0 - 31 (32 bit)
access : read-write

MADDR2 : RSA DMA Middle Address Register2 The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator.
bits : 0 - 31 (32 bit)
access : read-write

MADDR3 : RSA DMA Middle Address Register3 The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator.
bits : 0 - 31 (32 bit)
access : read-write

MADDR4 : RSA DMA Middle Address Register4 The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator.
bits : 0 - 31 (32 bit)
access : read-write

MADDR5 : RSA DMA Middle Address Register5 The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator.
bits : 0 - 31 (32 bit)
access : read-write

MADDR6 : RSA DMA Middle Address Register6 The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator.
bits : 0 - 31 (32 bit)
access : read-write

BUSY : RSA Accelerator Busy Flag Remember to clear RSA interrupt flag after RSA accelerator finished.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DMABUSY : RSA DMA Busy Flag
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUSERR : RSA DMA Access Bus Error Flag
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CTLERR : RSA Control Register Error Flag Note: If the error combination of control is used even though START(CRYPTO_RSA_CTL[0]) is not set to 1, CTLERR is still set to 1.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

KSERR : RSA Engine Access Key Store Error Flag
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

NUM : Read Key Number The key number is sent to key store
bits : 0 - 4 (5 bit)
access : write-only

RSRC : Read Key Source
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

RSSRC : Read Key Store Source
bits : 6 - 7 (2 bit)
access : write-only

Enumeration:

End of enumeration elements list.

BKNUM : Read Exponent Blind Key Number The key number is sent to key store, and its destination always be the SRAM of key store. CPU can't read the exponent blind key. Note: Use this key number only when executing SCA protection but no-CRT mode.
bits : 8 - 12 (5 bit)
access : write-only

NUM0 : Key Number0 The key number is generated by key store, RSA can get complete p by key number in Key Store while operating. Note: The size of this key as half key length.
bits : 0 - 4 (5 bit)
access : read-write

NUM1 : Key Number1 The key number is generated by key store, RSA can get complete q by key number in Key Store while operating. Note: The size of this key as half key length.
bits : 8 - 12 (5 bit)
access : read-write

NUM2 : Key Number2 The key number is generated by key store, RSA can get or store the intermediate temporary value by key number in Key Store while operating. Note: The size of this key as key length.
bits : 16 - 20 (5 bit)
access : read-write

NUM3 : Key Number3 The key number is generated by key store, RSA can get or store the intermediate temporary value by key number in Key Store while operating. Note: The size of this key as key length.
bits : 24 - 28 (5 bit)
access : read-write

NUM4 : Key Number4 The key number is generated by key store, RSA can get or store the intermediate temporary value by key number in Key Store while operating. Note: The size of this key as half key length.
bits : 0 - 4 (5 bit)
access : read-write

NUM5 : Key Number5 The key number is generated by key store, RSA can get or store the intermediate temporary value by key number in Key Store while operating. Note: The size of this key as half key length.
bits : 8 - 12 (5 bit)
access : read-write

NUM6 : Key Number6 The key number is generated by key store, RSA can get or store the intermediate temporary value by key number in Key Store while operating. Note: The size of this key as key length.
bits : 16 - 20 (5 bit)
access : read-write

NUM7 : Key Number7 The key number is generated by key store, RSA can get or store the intermediate temporary value by key number in Key Store while operating. Note: The size of this key as key length.
bits : 24 - 28 (5 bit)
access : read-write

SADDR0 : RSA DMA Source Address Register0 The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. This register is stored in the address of RSA the Base of Exponentiation (M).
bits : 0 - 31 (32 bit)
access : read-write

SADDR1 : RSA DMA Source Address Register1 The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. This register is stored in the address of RSA the Base of Modulus Operation (N).
bits : 0 - 31 (32 bit)
access : read-write