Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
TRNG Control Register and Status
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNGEN : Random Number Generator Enable Bit
This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit is set to 1 and READY (TRNG_CTL[7]) bit becames 1.
Note: TRNGEN is an enable bit of digital part. When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
TRNG Disabled
#1 : 1
TRNG Enabled
End of enumeration elements list.
DVIF : Data Valid (Read Only)
Note: This bit is cleared to '0' by reading TRNG_DATA.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data is not valid. Reading from RNGD returns 0x00000000
#1 : 1
Data is valid. A valid random number can be read form RNGD
End of enumeration elements list.
CLKPSC : Clock Prescaler
The CLKP is the peripheral clock frequency range for the selected value. The CLKP must be higher than or equal to the actual peripheral clock frequency (for correct random bit generation). To change the CLKP contents, first set TRNGEN bit to 0 and then change CLKP finally, set TRNGEN bit to 1 to re-enable the TRNG module.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
#0000 : 0
80 ~ 100 MHz
#0001 : 1
60 ~ 80 MHz
#0010 : 2
50 ~60 MHz
#0011 : 3
40 ~50 MHz
#0100 : 4
30 ~40 MHz
#0101 : 5
25 ~30 MHz
#0110 : 6
20 ~25 MHz
#0111 : 7
15 ~20 MHz
#1000 : 8
12 ~15 MHz
#1001 : 9
9 ~12 MHz
#1010 : 10
7 ~9 MHz
#1011 : 11
6 ~7 MHz
#1100 : 12
5 ~6 MHz
#1101 : 13
4 ~5 MHz
#1111 : 15
Reserved.
End of enumeration elements list.
DVIEN : Data Valid Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
READY : Random Number Generator Ready (Read Only)
After ACT (TRNG_ACT[7]) bit is set, the READY bit becomes 1 after a delay of 90us~120us.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
RNG is not ready or not activated
#1 : 1
RNG is ready to be enabled
End of enumeration elements list.
SEEDGEN : Random Number Seed Generator Enable Bit [for TRNG+PRNG]
This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit is set to 1 and READY (TRNG_CTL[7]) bit becomes 1.
Note: If users want to execute TRNG+PRNG mode, they should set SEEDGEN to 1. When SEEDGEN is set to 1, users cannot read the data from TRNG Data Register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Seed generator Disabled
#1 : 1
Seed generator Enabled
End of enumeration elements list.
SEEDRDY : Random Number Seed Ready (Read Only) [for TRNG+PRNG]
Note 1: This bit is cleared to '0' when SEEDGEN is 1.
Note 2: If SEEDRDY becomes 1, then SEEDGEN will be cleared to 0.
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
Seed is not ready or not activated
#1 : 1
Seed is ready for PRNG
End of enumeration elements list.
Reversed : Reversed
bits : 10 - 31 (22 bit)
access : read-write
TRNG Data Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Random Number Generator Data (Read Only)
The DATA stores the random number generated by TRNG and can be read only once.
bits : 0 - 7 (8 bit)
access : read-only
TRNG Activation Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : Random Number Generator Activation
After enabling the ACT bit, it will activate the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1.
Note: ACT is an enable bit of analog part. When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TRNG inactive
#1 : 1
TRNG active
End of enumeration elements list.
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