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LCD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :

Registers

LCD_CTL

LCD_PKGSEL

LCD_STS

LCD_INTEN

LCD_DATA00

LCD_DATA01

LCD_DATA02

LCD_DATA03

LCD_DATA04

LCD_DATA05

LCD_DATA06

LCD_DATA07

LCD_PCTL

LCD_DATA08

LCD_DATA09

LCD_DATA10

LCD_FCTL

LCD_DCTL


LCD_CTL

LCD Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_CTL LCD_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN SYNC

EN : LCD Display Enable Bit Note 1: When user writes 1 to this bit, the LCD Controller needs some synchronizing time to completely enable the LCD display function. Before that, the read value of this bit is still 0. Note 2: When user writes 0 to this bit, the LCD Controller needs some synchronizing time to completely disable the LCD display function. Before that, the read value of this bit is still 1.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

LCD display function Disabled

#1 : 1

LCD display function Enabled

End of enumeration elements list.

SYNC : LCD Enable/Disable Synchronizing Indicator (Read Only) When user writes 0/1 to EN (LCD_CTL[0]), the LCD Controller needs some synchronizing time to completely disable/enable the LCD display function. During this time, this bit keeps at 1. Note 1: The synchronizing time to enable LCD display function is not constant. It is between one and two cycles of CLKLCD. Note 2: The LCD display function cannot be disabled until the end of a frame. Thus, the maximum synchronizing time to disable LCD display function could be as long as one frame time.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

LCD display function is completely Disabled/Enabled

#1 : 1

LCD display function is not yet completely Disabled/Enabled

End of enumeration elements list.


LCD_PKGSEL

LCD Package Selection Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_PKGSEL LCD_PKGSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKG

PKG : Device Package Type Selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

128-Pin Package

#1 : 1

64-Pin Package

End of enumeration elements list.


LCD_STS

LCD Status Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_STS LCD_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCEF FEF CTOF CTIME

FCEF : End of Frame Counting Flag This flag is automatically set by hardware at the end of a frame, and the frame counter value must be equal to FCV (LCD_FCTL[17:8], Frame Counting Value). Note 1: User can clear this bit by writing 1 to it. Note 2: For type B waveform, this flag is set only at the end of an odd frame.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

End of Frame Counting did not occur

#1 : 1

End of Frame Counting occurred

End of enumeration elements list.

FEF : End of Frame Flag This flag is automatically set by hardware at the end of a frame. Note 1: User can clear this bit by writing 1 to it. Note 2: For type B waveform, this flag is set only at the end of an odd frame.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

End of Frame did not occur

#1 : 1

End of Frame occurred

End of enumeration elements list.

CTOF : Charging Timeout Flag This flag is automatically set by hardware when the charging timer reaches the timeout value. Note: User can clear this bit by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Charging Timeout did not occur

#1 : 1

Charging Timeout occurred

End of enumeration elements list.

CTIME : Charging Timer Value (Read Only) The field contains the value of the charging timer. It records the charging time of the charge pump. The charging timer stops counting when the charge pump stops charging or a timeout occurs. At this moment, the hardware dumps the current charging timer value into this field.
bits : 16 - 28 (13 bit)
access : read-only


LCD_INTEN

LCD Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_INTEN LCD_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCEIEN FEIEN CTOIEN

FCEIEN : End of Frame Counting Interrupt Enable Bit An interrupt occurs at the end of a frame, and the frame counter value must be equal to FCV (LCD_FCTL[17:8], Frame Counting Value). Note: For type B waveform, the interrupt occurs only at the end of an odd frame.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

End of Frame Counting Interrupt Disabled

#1 : 1

End of Frame Counting Interrupt Enabled

End of enumeration elements list.

FEIEN : End of Frame Interrupt Enable Bit An interrupt occurs at the end of a frame. Note: For type B waveform, the interrupt occurs only at the end of an odd frame.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

End of Frame Interrupt Disabled

#1 : 1

End of Frame Interrupt Enabled

End of enumeration elements list.

CTOIEN : Charging Timeout Interrupt Enable Bit An interrupt occurs when the charging timer reaches the timeout value.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Charging Timeout Interrupt Disabled

#1 : 1

Charging Timeout Interrupt Enabled

End of enumeration elements list.


LCD_DATA00

LCD Segment Display Data Register 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_DATA00 LCD_DATA00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DD0 DD1 DD2 DD3

DD0 : Display Data of Segments S, where S is 4 x N + 0, and N is 0, 1, 2, ..., 10 Each bit specifies the brightness of each pixel in a segment. LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : 0

The pixel is light

1 : 1

The pixel is dark

End of enumeration elements list.

DD1 : Display Data of Segments S, where S is 4 x N + 1, and N is 0, 1, 2, ..., 10 Each bit specifies the brightness of each pixel in a segment. LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used.
bits : 8 - 15 (8 bit)
access : read-write

Enumeration:

0 : 0

The pixel is light

1 : 1

The pixel is dark

End of enumeration elements list.

DD2 : Display Data of Segments S, where S is 4 x N + 2, and N is 0, 1, 2, ..., 10 Each bit specifies the brightness of each pixel in a segment. LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used.
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0 : 0

The pixel is light

1 : 1

The pixel is dark

End of enumeration elements list.

DD3 : Display Data of Segments S, where S is 4 x N + 3, and N is 0, 1, 2, ..., 10 Each bit specifies the brightness of each pixel in a segment. LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used.
bits : 24 - 31 (8 bit)
access : read-write

Enumeration:

0 : 0

The pixel is light

1 : 1

The pixel is dark

End of enumeration elements list.


LCD_DATA01

LCD Segment Display Data Register 1
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_DATA01 LCD_DATA01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCD_DATA02

LCD Segment Display Data Register 2
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_DATA02 LCD_DATA02 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCD_DATA03

LCD Segment Display Data Register 3
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_DATA03 LCD_DATA03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCD_DATA04

LCD Segment Display Data Register 4
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_DATA04 LCD_DATA04 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCD_DATA05

LCD Segment Display Data Register 5
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_DATA05 LCD_DATA05 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCD_DATA06

LCD Segment Display Data Register 6
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_DATA06 LCD_DATA06 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCD_DATA07

LCD Segment Display Data Register 7
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_DATA07 LCD_DATA07 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCD_PCTL

LCD Panel Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_PCTL LCD_PCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIAS DUTY TYPE INV FREQDIV CPVSEL CPVTUNE

BIAS : LCD Bias Level Selection This field is used to select the bias level.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : 0

Reserved.

1 : 1

1/2 Bias

2 : 2

1/3 Bias

3 : 3

1/4 Bias

End of enumeration elements list.

DUTY : LCD Duty Ratio Selection This field is used to select the duty ratio.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : 0

1/1 Duty

1 : 1

1/2 Duty

2 : 2

1/3 Duty

3 : 3

1/4 Duty

4 : 4

1/5 Duty

5 : 5

1/6 Duty

6 : 6

1/7 Duty

7 : 7

1/8 Duty

End of enumeration elements list.

TYPE : LCD Waveform Type Selection This bit is used to select the waveform type.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Type A

#1 : 1

Type B

End of enumeration elements list.

INV : LCD Waveform Inverse This bit is used to set the inverse LCD waveform.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

COM/SEG waveform is normal

#1 : 1

COM/SEG waveform is inversed

End of enumeration elements list.

FREQDIV : LCD Operating Frequency Divider The field is used to divide CLKLCD to generate the LCD operating frequency.
bits : 8 - 17 (10 bit)
access : read-write

CPVSEL : LCD Operating Voltage Select This field is used to select the LCD operating voltage. Note: This field is meaningful only if the VLCD source is the charge pump. Otherwise, this field is ignored.
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

0 : 0

2.6 V

1 : 1

2.8 V

2 : 2

3.0 V

3 : 3

3.2 V

4 : 4

3.4 V

5 : 5

3.6 V

End of enumeration elements list.

CPVTUNE : LCD Operating Voltage Fine Tuning This field is used to fine-tune the LCD operating voltage. Note 1: A unit of voltage is about 0.03 V. Note 2: This field is meaningful only if the VLCD source is the charge pump. Otherwise, this field is ignored.
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0 : 0

No tuning

1 : 1

decrease by 1 unit of voltage

2 : 2

decrease by 2 units of voltage

3 : 3

decrease by 3 units of voltage

4 : 4

decrease by 4 units of voltage

5 : 5

decrease by 5 units of voltage

6 : 6

decrease by 6 units of voltage

7 : 7

decrease by 7 units of voltage

8 : 8

increase by 8 units of voltage

9 : 9

increase by 7 units of voltage

10 : 10

increase by 6 units of voltage

11 : 11

increase by 5 units of voltage

12 : 12

increase by 4 units of voltage

13 : 13

increase by 3 units of voltage

14 : 14

increase by 2 units of voltage

15 : 15

increase by 1 unit of voltage

End of enumeration elements list.


LCD_DATA08

LCD Segment Display Data Register 8
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_DATA08 LCD_DATA08 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCD_DATA09

LCD Segment Display Data Register 9
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_DATA09 LCD_DATA09 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCD_DATA10

LCD Segment Display Data Register 10
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_DATA10 LCD_DATA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCD_FCTL

LCD Frame Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_FCTL LCD_FCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLINK FCV NFTIME NFNUM

BLINK : LCD Blinking Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

LCD blinking function Disabled

#1 : 1

LCD blinking function Enabled

End of enumeration elements list.

FCV : Frame Counting Value This field indicates the maximum value that the frame counter can reach. Note 1: The frame counter automatically increases by 1 at the end of every frame. When the counter reaches FCV, it will recounts from 0 at the end of the next frame. At this moment, the hardware sets a dedicated flag to 1, and triggers a dedicated interrupt if it is enabled. Note 2: For type B waveform, the frame counter increases at the end of odd frames, not even frames.
bits : 8 - 17 (10 bit)
access : read-write

NFTIME : Null Frame Time This field is used to configure the length of a null frame. One null frame time is (1 / FLCD) x NFTIME. Note: All COM and SEG output voltages are 0 V during a null frame.
bits : 24 - 27 (4 bit)
access : read-write

NFNUM : Number of Frames Inserted By One Null Frame This field is used to specify the number of continuous normal frames inserted by one null frame. The number of continuous normal frames is (NFNUM + 1) frames.
bits : 28 - 31 (4 bit)
access : read-write


LCD_DCTL

LCD Driving Control Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCD_DCTL LCD_DCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSRC RESMODE BUFEN PSVEN PSVREV PSVT1 PSVT2 CTOTIME

VSRC : LCD Operating Voltage Source Note: Whenever the LCD controller is disabled, all VLCD sources are automatically cut off.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : 0

VLCD Power

1 : 1

AVDD Power

2 : 2

Built-In Charge Pump

3 : 3

None

End of enumeration elements list.

RESMODE : Resistive Network Driving Mode
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Low-Drive Mode

#1 : 1

High-Drive Mode

End of enumeration elements list.

BUFEN : Voltage Buffer Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Voltage Buffer Disabled

#1 : 1

Voltage Buffer Enabled

End of enumeration elements list.

PSVEN : Power Saving Mode Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power Saving Mode Disabled

#1 : 1

Power Saving Mode Enabled

End of enumeration elements list.

PSVREV : Power Saving Timing Reverse When the timing is reversed, the original power saving period becomes no power saving, and the original no power saving period becomes power saving.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timing of power saving is normal

#1 : 1

Timing of power saving is reversed

End of enumeration elements list.

PSVT1 : Power Saving 'Enable Time' Setting The 'Enable Time' of the power saving mode is calculated as
bits : 8 - 11 (4 bit)
access : read-write

PSVT2 : Power Saving 'On Time' Setting The 'On Time' of the power saving mode is calculated as
bits : 12 - 15 (4 bit)
access : read-write

CTOTIME : Charging Timer Timeout Time This field is used to specify the timeout value for the charging timer. When the charging timer reaches this timeout value, a status bit or an interrupt will occur. The timeout is calculated by the following formula:
bits : 16 - 28 (13 bit)
access : read-write



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