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DAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

Registers

DAC0_CTL

DAC0_STATUS

DAC0_TCTL

DAC0_SWTRG

DAC1_CTL

DAC1_SWTRG

DAC1_DAT

DAC1_DATOUT

DAC1_STATUS

DAC1_TCTL

DAC0_DAT

DAC0_DATOUT


DAC0_CTL

DAC0 Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_CTL DAC0_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACEN DACIEN DMAEN DMAURIEN TRGEN TRGSEL BYPASS LALIGN ETRGSEL BWSEL GRPEN

DACEN : DAC Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC Disabled

#1 : 1

DAC Enabled

End of enumeration elements list.

DACIEN : DAC Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC interrupt Disabled

#1 : 1

DAC interrupt Enabled

End of enumeration elements list.

DMAEN : DMA Mode Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA mode Disabled

#1 : 1

DMA mode Enabled

End of enumeration elements list.

DMAURIEN : DMA Under-run Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA under-run interrupt Disabled

#1 : 1

DMA under-run interrupt Enabled

End of enumeration elements list.

TRGEN : Trigger Mode Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC event trigger mode Disabled

#1 : 1

DAC event trigger mode Enabled

End of enumeration elements list.

TRGSEL : Trigger Source Selection
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

#000 : 0

Software trigger

#001 : 1

External pin DAC0_ST trigger

#010 : 2

Timer 0 trigger

#011 : 3

Timer 1 trigger

#100 : 4

Timer 2 trigger

#101 : 5

Timer 3 trigger

#110 : 6

EPWM0 trigger

#111 : 7

EPWM1 trigger

End of enumeration elements list.

BYPASS : Bypass Buffer Mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Output voltage buffer Enabled

#1 : 1

Output voltage buffer Disabled

End of enumeration elements list.

LALIGN : DAC Data Left-aligned Enabled Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Right alignment

#1 : 1

Left alignment

End of enumeration elements list.

ETRGSEL : External Pin Trigger Selection
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

Low level trigger

#01 : 1

High level trigger

#10 : 2

Falling edge trigger

#11 : 3

Rising edge trigger

End of enumeration elements list.

BWSEL : DAC Data Bit-width Selection
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

Data is 12 bits

#01 : 1

Data is 8 bits

End of enumeration elements list.

GRPEN : DAC Group Mode Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC0 and DAC1 are not grouped

#1 : 1

DAC0 and DAC1 are grouped

End of enumeration elements list.


DAC0_STATUS

DAC0 Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_STATUS DAC0_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINISH DMAUDR BUSY

FINISH : DAC Conversion Complete Finish Flag Note: This bit is set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC is in conversion state

#1 : 1

DAC conversion finish

End of enumeration elements list.

DMAUDR : DMA Under-run Interrupt Flag Note: User writes 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No DMA under-run error condition occurred

#1 : 1

DMA under-run error condition occurred

End of enumeration elements list.

BUSY : DAC Busy Flag (Read Only)
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

DAC is ready for next conversion

#1 : 1

DAC is busy in conversion

End of enumeration elements list.


DAC0_TCTL

DAC0 Timing Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_TCTL DAC0_TCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETTLET

SETTLET : DAC Output Settling Time User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. For example, DAC controller clock speed is 80 MHz and DAC conversion settling time is 1 us, SETTLET value must be greater than 0x50.
bits : 0 - 9 (10 bit)
access : read-write


DAC0_SWTRG

DAC0 Software Trigger Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_SWTRG DAC0_SWTRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRG

SWTRG : Software Trigger Note: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically reading this bit will always get 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Software trigger Disabled

#1 : 1

Software trigger Enabled

End of enumeration elements list.


DAC1_CTL

DAC1 Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_CTL DAC1_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACEN DACIEN DMAEN DMAURIEN TRGEN TRGSEL BYPASS LALIGN ETRGSEL BWSEL

DACEN : DAC Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC Disabled

#1 : 1

DAC Enabled

End of enumeration elements list.

DACIEN : DAC Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC interrupt Disabled

#1 : 1

DAC interrupt Enabled

End of enumeration elements list.

DMAEN : DMA Mode Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA mode Disabled

#1 : 1

DMA mode Enabled

End of enumeration elements list.

DMAURIEN : DMA Under-run Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA under-run interrupt Disabled

#1 : 1

DMA under-run interrupt Enabled

End of enumeration elements list.

TRGEN : Trigger Mode Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC event trigger mode Disabled

#1 : 1

DAC event trigger mode Enabled

End of enumeration elements list.

TRGSEL : Trigger Source Selection
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

#000 : 0

Software trigger

#001 : 1

External pin DAC1_ST trigger

#010 : 2

Timer 0 trigger

#011 : 3

Timer 1 trigger

#100 : 4

Timer 2 trigger

#101 : 5

Timer 3 trigger

#110 : 6

EPWM0 trigger

#111 : 7

EPWM1 trigger

End of enumeration elements list.

BYPASS : Bypass Buffer Mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Output voltage buffer Enabled

#1 : 1

Output voltage buffer Disabled

End of enumeration elements list.

LALIGN : DAC Data Left-aligned Enable Control
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Right alignment

#1 : 1

Left alignment

End of enumeration elements list.

ETRGSEL : External Pin Trigger Selection
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

Low level trigger

#01 : 1

High level trigger

#10 : 2

Falling edge trigger

#11 : 3

Rising edge trigger

End of enumeration elements list.

BWSEL : DAC Data Bit-width Selection
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

Data is 12 bits

#01 : 1

Data is 8 bits

End of enumeration elements list.


DAC1_SWTRG

DAC1 Software Trigger Control Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_SWTRG DAC1_SWTRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRG

SWTRG : Software Trigger Note: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically Reading this bit will always get 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Software trigger Disabled

#1 : 1

Software trigger Enabled

End of enumeration elements list.


DAC1_DAT

DAC1 Data Holding Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_DAT DAC1_DAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACDAT

DACDAT : DAC 12-bit Holding Data These bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC1_DAT[3:0] in left-alignment mode and DAC1_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware. 12 bit left alignment: user has to load data into DAC1_DAT[15:4] bits. 12 bit right alignment: user has to load data into DAC1_DAT[11:0] bits.
bits : 0 - 15 (16 bit)
access : read-write


DAC1_DATOUT

DAC1 Data Output Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC1_DATOUT DAC1_DATOUT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATOUT

DATOUT : DAC 12-bit Output Data These bits are current digital data for DAC output conversion. It is loaded from DAC1_DAT register and user cannot write it directly.
bits : 0 - 11 (12 bit)
access : read-only


DAC1_STATUS

DAC1 Status Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_STATUS DAC1_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINISH DMAUDR BUSY

FINISH : DAC Conversion Complete Finish Flag Note: This bit set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC is in conversion state

#1 : 1

DAC conversion finished

End of enumeration elements list.

DMAUDR : DMA Under-run Interrupt Flag Note: User writes 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No DMA under-run error condition occurred

#1 : 1

DMA under-run error condition occurred

End of enumeration elements list.

BUSY : DAC Busy Flag (Read Only)
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

DAC is ready for the next conversion

#1 : 1

DAC is busy in conversion

End of enumeration elements list.


DAC1_TCTL

DAC1 Timing Control Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC1_TCTL DAC1_TCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETTLET

SETTLET : DAC Output Settling Time User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. For example, DAC controller clock speed is 80 MHz and DAC conversion settling time is 1 us, SETTLET value must be greater than 0x50.
bits : 0 - 9 (10 bit)
access : read-write


DAC0_DAT

DAC0 Data Holding Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0_DAT DAC0_DAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACDAT

DACDAT : DAC 12-bit Holding Data These bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC0_DAT[3:0] in left-alignment mode and DAC0_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware. 12 bit left alignment: user has to load data into DAC0_DAT[15:4] bits. 12 bit right alignment: user has to load data into DAC0_DAT[11:0] bits.
bits : 0 - 15 (16 bit)
access : read-write


DAC0_DATOUT

DAC0 Data Output Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC0_DATOUT DAC0_DATOUT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATOUT

DATOUT : DAC 12-bit Output Data These bits are current digital data for DAC output conversion. It is loaded from DAC0_DAT register and user cannot write it directly.
bits : 0 - 11 (12 bit)
access : read-only



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