SYS_PDID (PDID)

SYS_IPRST2 (IPRST2)

SYS_REGLCTL (REGLCTL)

SYS_MIRCTRIMCTL (MIRCTRIMCTL)

SYS_MIRCTRIMIEN (MIRCTRIMIEN)

SYS_MIRCTRIMSTS (MIRCTRIMSTS)

SYS_ALTCTL (ALTCTL)

SYS_BODCTL (BODCTL)

SYS_IVSCTL (IVSCTL)

SYS_PORCTL1 (PORCTL1)

SYS_PLCTL (PLCTL)

SYS_PLSTS (PLSTS)

SYS_PORCTL0 (PORCTL0)

SYS_GPA_MFPL (GPA_MFPL)

SYS_GPA_MFPH (GPA_MFPH)

SYS_GPB_MFPL (GPB_MFPL)

SYS_GPB_MFPH (GPB_MFPH)

SYS_RSTSTS (RSTSTS)

SYS_GPC_MFPL (GPC_MFPL)

SYS_GPC_MFPH (GPC_MFPH)

SYS_GPF_MFPL (GPF_MFPL)

SYS_GPF_MFPH (GPF_MFPH)

SYS_IPRST0 (IPRST0)

SYS_GPA_MFOS (GPA_MFOS)

SYS_GPB_MFOS (GPB_MFOS)

SYS_GPC_MFOS (GPC_MFOS)

SYS_GPF_MFOS (GPF_MFOS)

SYS_IPRST1 (IPRST1)

SYS_MODCTL (MODCTL)

SYS_SRAM_BISTCTL (SRAM_BISTCTL)

SYS_SRAM_BISTSTS (SRAM_BISTSTS)

SYS_HIRCTRIMCTL (HIRCTRIMCTL)

SYS_HIRCTRIMIEN (HIRCTRIMIEN)

SYS_HIRCTRIMSTS (HIRCTRIMSTS)

PDID : Part Device Identification Number (Read Only) This register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only

USCI0RST : USCI0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWM0RST : BPWM0 Controller Reset
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REGLCTL : Register Lock Control Code Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. Register Lock Control Disable Index The Protected registers are: NMIEN address 0x4000_0300 FMC_ISPCTL address 0x4000_C000 (Flash ISP Control register) FMC_ISPTRG address 0x4000_C010 (ISP Trigger Control register) FMC_ISPSTS address 0x4000_C040 WDT_CTL address 0x4004_0000 FMC_FTCTL address 0x4000_5018 FMC_ICPCMD address 0x4000_501C EADC_TEST address 0x4004_3200 AHBMCTL address 0x4000_0400 SYS_IPRST0 address 0x4000_0008 SYS_BODCTL address 0x4000_0018 SYS_PORCTL0 address 0x4000_0024 SYS_SRAM_BISTCTL address 0x4000_00D0 SYS_PORCTL1 address 0x4000_1EC CLK_PWRCTL address 0x4000_0200 CLK_APBCLK0[0] address 0x4000_0208 CLK_CLKSEL0 address 0x4000_0110 CLK_CLKSEL1[3:0] address 0x4000_0214 CLK_PLLCTL address 0x4000_0240 CLK_PMUCTL address 0x4000_0290 CLK_HXTFSEL address 0x4000_02B4
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQSEL : Trim Frequency Selection This field indicates the target frequency of medium speed RC oscillator (MIRC) auto trim. During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop Selection This field defines that trim value calculation is based on how many reference clocks. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RETRYCNT : Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked. Once the MIRC locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and frequency of MIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOUNDEN : Boundary Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REFCKSEL : Reference Clock Selection
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOUNDARY : Boundary Selection Fill the boundary range from 0x1 to 0x1F. 0x0 is reserved. Note: This field is effective only when the BOUNDEN(SYS_MIRCTRIMCTL[9]) is enabled.
bits : 16 - 20 (5 bit)
access : read-write

TFALIEN : Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL(SYS_ MIRTRIMCTL[1:0]). If this bit is high and TFAILIF(SYS_ MIRCTRIMSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that MIRC trim value update limitation count reached.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKEIEN : Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccurate during auto trim operation. If this bit is set to1, and CLKERRIF(SYS_MIRCTRIMSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccurate.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQLOCK : MIRC Frequency Lock Status This bit indicates the MIRC frequency is locked. This is a status bit and doesn't trigger any interrupt. Write 1 to clear this to 0. This bit will be set automatically if the frequency is locked and the RC_TRIM is enabled. Note: Reset by power on reset.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIF : Trim Failure Interrupt Status This bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency is still not locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_MIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN(SYS_MIRCTRIMIEN[1]) is high, an interrupt will be triggered to notify that MIRC trim value update limitation count reached. Write 1 to clear this to 0. Note: Reset by power on reset.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERIF : Clock Error Interrupt Status When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal medium speed RC oscillator (MIRC) is shift larger to unreasonable value, this bit will be set and be an indicate that clock frequency is inaccurate. Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_MIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_MIRCTRIMCTL[8]) is set to 1. If this bit is set and CLKEIEN(SYS_MIRCTRIMIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccurate. Write 1 to clear this to 0. Note: Reset by power on reset.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVBDIF : Over Boundary Status When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. Note: Write 1 to clear this flag.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CANFD0_PDEN : CANFD0 Power Down Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CANFD0CKSTP : CANFD0 Clock Stop Acknowledgement (Read Only)
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BODEN : Brown-out Detector Enable Bit (Write Protect) The default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]). Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by power on reset.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRSTEN : Brown-out Reset Enable Bit (Write Protect) The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit. Note 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. Note 3: Reset by power on reset.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODIF : Brown-out Detector Interrupt Flag Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODLPM : Brown-out Detector Low Power Mode (Write Protect) Note 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. Note 2: For BOD low power mode to be active, LVREN must be set to 1 Note 3: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODOUT : Brown-out Detector Output Status It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function is disabled. This bit always responds 0000.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVREN : Low Voltage Reset Enable Bit (Write Protect) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. Note 1: After enabling the bit, the LVR function will be active with 3ms delay for LVR output stable (default). Note 2: For BOD low power mode to be active, this bit must be set to 1. Note 3: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODDGSEL : Brown-out Detector Output De-glitch Time Select (Write Protect) Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRDGSEL : LVR Output De-glitch Time Select (Write Protect) Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. Note 2: The MIRC is enabled automatically when LVRDGSEL is not 000 and LVREN is 1.
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODVL : Brown-out Detector Threshold Voltage Selection (Write Protect) The default value is set by Flash controller user configuration register CBOV (CONFIG0 [23:21]). Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by power on reset.
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VTEMPEN : Temperature Sensor Enable Bit This bit is used to enable/disable temperature sensor function. .
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POROFF : Power-on Reset Enable Bit (Write Protect) After powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field. The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write

PLSEL : Power Level Select(Write Protect) Note : When system is at PL3, HCLK clock has to come from LXT or LIRC.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLCBUSY : Power Level Change Busy Bit (Read Only) This bit is set by hardware when power level is changing. After power level change is completed, this bit will be cleared automatically by hardware.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CURPL : Current Power Level (Read Only) This bit field reflect the current power level. Note : When system is at PL3, HCLK clock has to come from LXT or LIRC.
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PORMASK : Power-on Reset Mask Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can mask internal POR signal to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write

PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PA1MFP : PA.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PA2MFP : PA.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PA3MFP : PA.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PA4MFP : PA.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PA5MFP : PA.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PA6MFP : PA.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PA7MFP : PA.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PA8MFP : PA.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PA9MFP : PA.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PA10MFP : PA.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PA11MFP : PA.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PA12MFP : PA.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PA13MFP : PA.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PA14MFP : PA.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PA15MFP : PA.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PB8MFP : PB.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PB9MFP : PB.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PB10MFP : PB.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PB11MFP : PB.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PB12MFP : PB.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PB13MFP : PB.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PB14MFP : PB.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PB15MFP : PB.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PORF : POR Reset Flag The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINRF : NRESET Pin Reset Flag The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRF : WDT Reset Flag The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. Note 1: Write 1 to clear this bit to 0. Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRF : LVR Reset Flag The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRF : BOD Reset Flag The BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRF : System Reset Flag The system reset flag is set by the 'Reset Signal' from the CortexM23Core to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMURF : PMU Reset Flag, The PMU reset flag is set by any reset signal when MCU is in power down state. Note: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURF : CPU Reset Flag The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M23 core and Flash Memory Controller (FMC). Note: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPULKRF : CPU Lockup Reset Flag Note 1: Write 1 to clear this bit to 0. Note 2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PC1MFP : PC.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PC2MFP : PC.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PC3MFP : PC.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PC4MFP : PC.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PC5MFP : PC.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PC6MFP : PC.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PC7MFP : PC.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PC8MFP : PC.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PC9MFP : PC.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PC10MFP : PC.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PC11MFP : PC.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PC12MFP : PC.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PC13MFP : PC.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PC14MFP : PC.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PC15MFP : PC.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PF0MFP : PF.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PF1MFP : PF.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PF2MFP : PF.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PF3MFP : PF.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PF4MFP : PF.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PF5MFP : PF.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PF6MFP : PF.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PF7MFP : PF.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PF8MFP : PF.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PF9MFP : PF.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PF10MFP : PF.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PF11MFP : PF.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PF12MFP : PF.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PF13MFP : PF.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PF14MFP : PF.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PF15MFP : PF.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

CHIPRST : Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload. For the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by power on reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURST : Processor Core One-shot Reset (Write Protect) Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMARST : PDMA Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCRST : CRC Calculation Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS0 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS1 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS2 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS3 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS4 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS5 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS6 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS7 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS8 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS9 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS10 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS11 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS12 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS13 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS14 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS15 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3RST : Timer3 Controller Reset
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1RST : I2C1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0RST : SPI0 Controller Reset
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART2RST : UART2 Controller Reset
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART3RST : UART3 Controller Reset
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART4RST : UART4 Controller Reset
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CANFD0RST : CANFD0 Controller Reset
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBDRST : USBD Controller Reset
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EADCRST : EADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRBIST : SRAM BIST Enable Bit (Write Protect) This bit enables BIST test for SRAM. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FMCBIST : FMC CACHE BIST Enable Bit (Write Protect) This bit enables BIST test for CACHE RAM. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBBIST : USB BIST Enable Bit (Write Protect) This bit enables BIST test for USB RAM Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CANFD0BIST : CANFD0 BIST Enable Bit (Write Protect) This bit enables BIST test for CANFD0 RAM. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMABIST : PDMA BIST Enable Bit (Write Protect) This bit enables BIST test for PDMA RAM. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRBISTEF : System SRAM BIST Fail Flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CR0BISTEF : CACHE0 SRAM BIST Fail Flag
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CR1BISTEF : CACHE1 SRAM BIST Fail Flag
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

USBBEF : USB SRAM BIST Fail Flag
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CANFD0BISTF : CANFD0 SRAM BIST Failed Flag
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PDMABISTF : PDMA SRAM BIST Failed Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SRBEND : SRAM BIST Test Finish
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CR0BEND : CACHE 0 SRAM BIST Test Finish
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CR1BEND : CACHE 1 SRAM BIST Test Finish
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

USBBEND : USB SRAM BIST Test Finish
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CANFD0END : CANFD0 SRAM BIST Test Finish
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PDMAEND : PDMA SRAM BIST Test Finish
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FREQSEL : Trim Frequency Selection This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim. During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop Selection This field defines that trim value calculation is based on how many reference clocks. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RETRYCNT : Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. Once the HIRC locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and frequency of HIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOUNDEN : Boundary Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REFCKSEL : Reference Clock Selection
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOUNDARY : Boundary Selection Fill the boundary range from 0x1 to 0x1F. 0x0 is reserved. Note: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enabled.
bits : 16 - 20 (5 bit)
access : read-write

TFALIEN : Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency is still not locked on target frequency set by FREQSEL(SYS_HIRCTRIMCTL[1:0]). If this bit is high and TFAILIF(SYS_HIRCTRIMSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count reached.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKEIEN : Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccurate during auto trim operation. If this bit is set to1, and CLKERRIF(SYS_HIRCTRIMSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccurate.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQLOCK : HIRC Frequency Lock Status This bit indicates the HIRC frequency is locked. This is a status bit and doesn't trigger any interrupt Write 1 to clear this to 0. This bit will be set automatically if the frequency is locked and the RC_TRIM is enabled. Note: Reset by power on reset.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIF : Trim Failure Interrupt Status This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency is still not locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN(SYS_HIRCTRIMIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count reached. Write 1 to clear this to 0. Note: Reset by power on reset.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERIF : Clock Error Interrupt Status When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccurate. Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTRIMCTL[8]) is set to 1. If this bit is set and CLKEIEN(SYS_HIRCTRIMIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. Note: Reset by power on reset.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVBDIF : Over Boundary Status When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. Note: Write 1 to clear this flag.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.