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CLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x70 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x90 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xB4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

CLK_PWRCTL (PWRCTL)

CLK_CLKSEL0 (CLKSEL0)

CLK_CLKSEL1 (CLKSEL1)

CLK_CLKSEL2 (CLKSEL2)

CLK_CLKSEL3 (CLKSEL3)

CLK_CLKDIV0 (CLKDIV0)

CLK_CLKDIV4 (CLKDIV4)

CLK_PCLKDIV (PCLKDIV)

CLK_AHBCLK (AHBCLK)

CLK_STATUS (STATUS)

CLK_CLKOCTL (CLKOCTL)

CLK_CLKDCTL (CLKDCTL)

CLK_CLKDSTS (CLKDSTS)

CLK_CDUPB (CDUPB)

CLK_CDLOWB (CDLOWB)

CLK_APBCLK0 (APBCLK0)

CLK_PMUCTL (PMUCTL)

CLK_HXTFSEL (HXTFSEL)

CLK_APBCLK1 (APBCLK1)


CLK_PWRCTL (PWRCTL)

System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PWRCTL CLK_PWRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTEN LXTEN HIRCEN LIRCEN PDWKDLY PDWKIEN PDWKIF PDEN MIRCEN HXTGAIN

HXTEN : HXT Enable Bit (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by powr on reset.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~32 MHz external high speed crystal (HXT) Disabled

#1 : 1

4~32 MHz external high speed crystal (HXT) Enabled

End of enumeration elements list.

LXTEN : LXT Enable Bit (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by RTC powr on reset.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external low speed crystal (LXT) Disabled

#1 : 1

32.768 kHz external low speed crystal (LXT) Enabled

End of enumeration elements list.

HIRCEN : HIRC Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

48 MHz internal high speed RC oscillator (HIRC) Disabled

#1 : 1

48 MHz internal high speed RC oscillator (HIRC) Enabled

End of enumeration elements list.

LIRCEN : LIRC Enable Bit (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: LIRC will also be forced on when 1. Power down and ~(CONFIG0[3] CONFIG0[4] ~CONFIG0[31] CONFIG0[30]) 2. Not power down and ~(CONFIG0[3] CONFIG0[4] CONFIG0[31])
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

38.4 kHz internal low speed RC oscillator (LIRC) Disabled

#1 : 1

38.4 kHz internal low speed RC oscillator (LIRC) Enabled

End of enumeration elements list.

PDWKDLY : Enable the Wake-up Delay Counter (Write Protect) When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip works at 4~32 MHz external high speed crystal oscillator (HXT), The delayed clock cycle is 512 clock cycles when chip works at 48 MHz internal high speed RC oscillator (HIRC) The delayed clock cycle is 32 clock cycles when chip works at 4 MHz internal median speed RC oscillator (MIRC) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock cycles delay Disabled

#1 : 1

Clock cycles delay Enabled

End of enumeration elements list.

PDWKIEN : Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power-down mode wake-up interrupt Disabled

#1 : 1

Power-down mode wake-up interrupt Enabled

End of enumeration elements list.

PDWKIF : Power-down Mode Wake-up Interrupt Status Set by 'Power-down wake-up event' indicates that resume from Power-down mode' The flag is set if any wake-up source is occurred. Refer to Power Modes and Wake-up Sources section. Note 1: Write 1 to clear the bit to 0. Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) is set to 1.
bits : 6 - 6 (1 bit)
access : read-write

PDEN : System Power-down Enable (Write Protect) When this bit is set to 1, Power-down mode is enabled, chip enters Power-down mode immediately after the PDEN bit set. When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. In Power-down mode, HXT ,MIRC and HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. In Power-down mode, the HCLK, PCLK0 and PCLK1 clocks are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip operating normally or chip in idle mode because of WFI command

#1 : 1

Chip enters Power-down mode instantly or wait CPU sleep command WFI

End of enumeration elements list.

MIRCEN : MIRC Enable Bit (Write Protect)
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

4 MHz internal high speed RC oscillator (MIRC) Disabled

#1 : 1

4 MHz internal high speed RC oscillator (MIRC) Enabled

End of enumeration elements list.

HXTGAIN : HXT Gain Control Bit (Write Protect) This is a protected register. Please refer to open lock sequence to program it. Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by power on reset.
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

HXT frequency 1~4 MHz

#001 : 1

HXT frequency 4~8 MHz

#010 : 2

HXT frequency 8~12 MHz

#011 : 3

HXT frequency 12~ 16 MHz

#100 : 4

HXT frequency 16~24 MHz

#101 : 5

HXT frequency 24~32 MHz

#110 : 6

HXT frequency 24~32 MHz

#111 : 7

HXT frequency 24~32 MHz

End of enumeration elements list.


CLK_CLKSEL0 (CLKSEL0)

Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL0 CLK_CLKSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKSEL STCLKSEL CANFD0SEL

HCLKSEL : HCLK Clock Source Selection (Write Protect) Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by power on reset.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT

#001 : 1

Clock source from LXT

#011 : 3

Clock source from LIRC

#101 : 5

Clock source from MIRC

#111 : 7

Clock source from HIRC

End of enumeration elements list.

STCLKSEL : Cortex-M23 SysTick Clock Source Selection (Write Protect) Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT

#001 : 1

Clock source from LXT

#010 : 2

Clock source from HXT/2

#011 : 3

Clock source from HCLK/2

#111 : 7

Clock source from HIRC/2

End of enumeration elements list.

CANFD0SEL : CANFD0 Clock Source Selection
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from HCLK

#1 : 1

Clock source from HXT

End of enumeration elements list.


CLK_CLKSEL1 (CLKSEL1)

Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL1 CLK_CLKSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTSEL WWDTSEL CLKOSEL TMR0SEL TMR1SEL TMR2SEL TMR3SEL UART0SEL UART1SEL

WDTSEL : Watchdog Timer Clock Source Selection (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: This bit is forced to 11 when CONFIG0[31] or CONFIG0[4] or CONFIG0[3] is 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Reserved.

#01 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#10 : 2

Clock source from HCLK/2048

#11 : 3

Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)

End of enumeration elements list.

WWDTSEL : Window Watchdog Timer Clock Source Selection (Write Protect)
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#10 : 2

Clock source from HCLK/2048

#11 : 3

Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)

End of enumeration elements list.

CLKOSEL : Clock Divider Clock Source Selection
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#010 : 2

Clock source from HCLK

#011 : 3

Clock source from 48 MHz internal high speed RC oscillator (HIRC)

#100 : 4

Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)

#101 : 5

Clock source from 4 MHz internal medium speed RC oscillator (MIRC)

#111 : 7

Clock source from USB SOF

End of enumeration elements list.

TMR0SEL : TIMER0 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#010 : 2

Clock source from PCLK0

#011 : 3

Clock source from external clock T0 pin

#101 : 5

Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)

#111 : 7

Clock source from 48 MHz internal high speed RC oscillator (HIRC)

End of enumeration elements list.

TMR1SEL : TIMER1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#010 : 2

Clock source from PCLK0

#011 : 3

Clock source from external clock T1 pin

#101 : 5

Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)

#111 : 7

Clock source from 48 MHz internal high speed RC oscillator (HIRC)

End of enumeration elements list.

TMR2SEL : TIMER2 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#010 : 2

Clock source from PCLK1

#011 : 3

Clock source from external clock T2 pin

#101 : 5

Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)

#111 : 7

Clock source from 48 MHz internal high speed RC oscillator (HIRC)

End of enumeration elements list.

TMR3SEL : TIMER3 Clock Source Selection
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#010 : 2

Clock source from PCLK1

#011 : 3

Clock source from external clock T3 pin

#101 : 5

Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)

#111 : 7

Clock source from 48 MHz internal high speed RC oscillator (HIRC)

End of enumeration elements list.

UART0SEL : UART0 Clock Source Selection
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#010 : 2

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#011 : 3

Clock source from 48 MHz internal high speed RC oscillator (HIRC)

#100 : 4

Clock source from PCLK0

#101 : 5

Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)

End of enumeration elements list.

UART1SEL : UART1 Clock Source Selection
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#010 : 2

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#011 : 3

Clock source from 48 MHz internal high speed RC oscillator (HIRC)

#100 : 4

Clock source from PCLK1

#101 : 5

Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)

End of enumeration elements list.


CLK_CLKSEL2 (CLKSEL2)

Clock Source Select Control Register 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL2 CLK_CLKSEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0SEL

SPI0SEL : SPI0 Clock Source Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#01 : 1

Reserved.

#10 : 2

Clock source from PCLK1

#11 : 3

Clock source from 48 MHz internal high speed RC oscillator (HIRC)

End of enumeration elements list.


CLK_CLKSEL3 (CLKSEL3)

Clock Source Select Control Register 3
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL3 CLK_CLKSEL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART4SEL UART2SEL UART3SEL

UART4SEL : UART4 Clock Source Selection
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#010 : 2

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#011 : 3

Clock source from 48 MHz internal high speed RC oscillator (HIRC)

#100 : 4

Clock source from PCLK0

#101 : 5

Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)

End of enumeration elements list.

UART2SEL : UART2 Clock Source Selection
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#010 : 2

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#011 : 3

Clock source from 48 MHz internal high speed RC oscillator (HIRC)

#100 : 4

Clock source from PCLK0

#101 : 5

Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)

End of enumeration elements list.

UART3SEL : UART3 Clock Source Selection
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~32 MHz external high speed crystal oscillator (HXT)

#010 : 2

Clock source from 32.768 kHz external low speed crystal oscillator (LXT)

#011 : 3

Clock source from 48 MHz internal high speed RC oscillator (HIRC)

#100 : 4

Clock source from PCLK1

#101 : 5

Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)

End of enumeration elements list.


CLK_CLKDIV0 (CLKDIV0)

Clock Divider Number Register 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDIV0 CLK_CLKDIV0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKDIV UART0DIV UART1DIV EADCDIV

HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source Note: This field is only reset by power on reset.
bits : 0 - 3 (4 bit)
access : read-write

UART0DIV : UART0 Clock Divide Number From UART0 Clock Source
bits : 8 - 11 (4 bit)
access : read-write

UART1DIV : UART1 Clock Divide Number From UART1 Clock Source
bits : 12 - 15 (4 bit)
access : read-write

EADCDIV : EADC Clock Divide Number From EADC Clock Source
bits : 16 - 23 (8 bit)
access : read-write


CLK_CLKDIV4 (CLKDIV4)

Clock Divider Number Register 4
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDIV4 CLK_CLKDIV4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART2DIV UART3DIV UART4DIV CANFD0DIV

UART2DIV : UART2 Clock Divide Number From UART2 Clock Source
bits : 0 - 3 (4 bit)
access : read-write

UART3DIV : UART3 Clock Divide Number From UART3 Clock Source
bits : 4 - 7 (4 bit)
access : read-write

UART4DIV : UART4 Clock Divide Number From UART4 Clock Source
bits : 8 - 11 (4 bit)
access : read-write

CANFD0DIV : CANFD0 Clock Divide Number From CANFD0 Clock Source
bits : 16 - 17 (2 bit)
access : read-write


CLK_PCLKDIV (PCLKDIV)

APB Clock Divider Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PCLKDIV CLK_PCLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB0DIV APB1DIV

APB0DIV : APB0 Clock DIvider APB0 clock can be divided from HCLK Others: Reserved.
bits : 0 - 2 (3 bit)
access : read-write

APB1DIV : APB1 Clock DIvider APB1 clock can be divided from HCLK Others: Reserved.
bits : 4 - 6 (3 bit)
access : read-write


CLK_AHBCLK (AHBCLK)

AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_AHBCLK CLK_AHBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMACKEN ISPCKEN EXSTCKEN CRCCKEN FMCIDLE CANFD0CKEN GPACKEN GPBCKEN GPCCKEN GPFCKEN

PDMACKEN : PDMA Controller Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA peripheral clock Disabled

#1 : 1

PDMA peripheral clock Enabled

End of enumeration elements list.

ISPCKEN : Flash ISP Controller Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Flash ISP peripheral clock Disabled

#1 : 1

Flash ISP peripheral clock Enabled

End of enumeration elements list.

EXSTCKEN : External System Tick Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

External System tick clock Disabled

#1 : 1

External System tick clock Enabled

End of enumeration elements list.

CRCCKEN : CRC Generator Controller Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRC peripheral clock Disabled

#1 : 1

CRC peripheral clock Enabled

End of enumeration elements list.

FMCIDLE : Flash Memory Controller Clock Enable Bit in IDLE Mode
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

FMC clock Disabled when chip is under IDLE mode in this case, PDMA cannot access FMC memory

#1 : 1

FMC clock Enabled when chip is under IDLE mode PDMA can access FMC memory

End of enumeration elements list.

CANFD0CKEN : CANFD0 Clock Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

CANFD0 clock Disabled

#1 : 1

CANFD0 clock Enabled

End of enumeration elements list.

GPACKEN : GPIOA Clock Enable Bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA port clock Disabled

#1 : 1

GPIOA port clock Enabled

End of enumeration elements list.

GPBCKEN : GPIOB Clock Enable Bit
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB port clock Disabled

#1 : 1

GPIOB port clock Enabled

End of enumeration elements list.

GPCCKEN : GPIOC Clock Enable Bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOC port clock Disabled

#1 : 1

GPIOC port clock Enabled

End of enumeration elements list.

GPFCKEN : GPIOF Clock Enable Bit
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOF port clock Disabled

#1 : 1

GPIOF port clock Enabled

End of enumeration elements list.


CLK_STATUS (STATUS)

Clock Status Monitor Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLK_STATUS CLK_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTSTB LXTSTB LIRCSTB HIRCSTB MIRCSTB CLKSFAIL

HXTSTB : HXT Clock Source Stable Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

4~32 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled

#1 : 1

4~32 MHz external high speed crystal oscillator (HXT) clock is stable and enabled

End of enumeration elements list.

LXTSTB : LXT Clock Source Stable Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled

End of enumeration elements list.

LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

38.4 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled

#1 : 1

38.4 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled

End of enumeration elements list.

HIRCSTB : HIRC Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

48 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled

#1 : 1

48 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled

End of enumeration elements list.

MIRCSTB : MIRC Clock Source Stable Flag (Read Only)
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

4 MHz internal mid speed RC oscillator (MIRC) clock is not stable or disabled

#1 : 1

4 MHz internal mid speed RC oscillator (MIRC) clock is stable and enabled

End of enumeration elements list.

CLKSFAIL : Clock Switching Fail Flag This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1. Note: Write 1 to clear the bit to 0.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Clock switching success

#1 : 1

Clock switching failure

End of enumeration elements list.


CLK_CLKOCTL (CLKOCTL)

Clock Output Control Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKOCTL CLK_CLKOCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQSEL DIV1EN CLK1HZEN

FREQSEL : Clock Output Frequency Selection The formula of output frequency is Fin is the input clock frequency. Fout is the frequency of divider output clock. N is the 4-bit value of FREQSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

DIV1EN : Clock Output Divide One Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock Output will output clock with source frequency divided by FREQSEL

#1 : 1

Clock Output will output clock with source frequency

End of enumeration elements list.

CLK1HZEN : Clock Output 1Hz Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

1 Hz clock output for 32.768 kHz frequency compensation Disabled

#1 : 1

1 Hz clock output for 32.768 kHz frequency compensation Enabled

End of enumeration elements list.


CLK_CLKDCTL (CLKDCTL)

Clock Fail Detector Control Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDCTL CLK_CLKDCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTFDEN HXTFIEN LXTFDEN LXTFIEN HXTFQDEN HXTFQIEN

HXTFDEN : HXT Clock Fail Detector Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled

#1 : 1

4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled

End of enumeration elements list.

HXTFIEN : HXT Clock Fail Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled

#1 : 1

4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled

End of enumeration elements list.

LXTFDEN : LXT Clock Fail Detector Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled

End of enumeration elements list.

LXTFIEN : LXT Clock Fail Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled

End of enumeration elements list.

HXTFQDEN : HXT Clock Frequency Range Detector Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled

#1 : 1

4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled

End of enumeration elements list.

HXTFQIEN : HXT Clock Frequency Range Detector Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled

#1 : 1

4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled

End of enumeration elements list.


CLK_CLKDSTS (CLKDSTS)

Clock Fail Detector Status Register
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDSTS CLK_CLKDSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTFIF LXTFIF HXTFQIF

HXTFIF : HXT Clock Fail Interrupt Flag (Write Protect) Note: Write 1 to clear the bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~32 MHz external high speed crystal oscillator (HXT) clock is normal

#1 : 1

4~32 MHz external high speed crystal oscillator (HXT) clock stops

End of enumeration elements list.

LXTFIF : LXT Clock Fail Interrupt Flag (Write Protect) Note: Write 1 to clear the bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock is normal

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) stops

End of enumeration elements list.

HXTFQIF : HXT Clock Frequency Range Detector Interrupt Flag (Write Protect) Note: Write 1 to clear the bit to 0.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~32 MHz external high speed crystal oscillator (HXT) clock frequency is normal

#1 : 1

4~32 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal

End of enumeration elements list.


CLK_CDUPB (CDUPB)

Clock Frequency Range Detector Upper Boundary Register
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CDUPB CLK_CDUPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPERBD

UPERBD : HXT Clock Frequency Range Detector Upper Boundary Value The bits define the maximum value of frequency range detector window. When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. Note :Frequency out of range will be asserted when HIRC_period*512 HXT_period*CLK_DUPB or HIRC_period*512 HXT_period*CLK_CDLOWB.
bits : 0 - 9 (10 bit)
access : read-write


CLK_CDLOWB (CDLOWB)

Clock Frequency Range Detector Lower Boundary Register
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CDLOWB CLK_CDLOWB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWERBD

LOWERBD : HXT Clock Frequency Range Detector Lower Boundary Value The bits define the minimum value of frequency range detector window. When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. Note :The frequency out of range will be asserted when HIRC_period*512 HXT_period*CLK_DUPB or HIRC_period*512 HXT_period*CLK_CDLOWB.
bits : 0 - 9 (10 bit)
access : read-write


CLK_APBCLK0 (APBCLK0)

APB Devices Clock Enable Control Register 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_APBCLK0 CLK_APBCLK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTCKEN RTCCKEN TMR0CKEN TMR1CKEN TMR2CKEN TMR3CKEN CLKOCKEN I2C0CKEN I2C1CKEN SPI0CKEN UART0CKEN UART1CKEN UART2CKEN UART3CKEN UART4CKEN USBDCKEN EADCCKEN

WDTCKEN : Watchdog Timer Clock Enable Bit (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: This bit is forced to 1 when CONFIG0[3] or CONFIG0[4] or CONFIG0[31] is 0. Note 3: Reset by power on reset or watchdog reset or software chip reset.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer clock Disabled

#1 : 1

Watchdog timer clock Enabled

End of enumeration elements list.

RTCCKEN : Real-time-clock APB Interface Clock Enable Bit This bit is used to control the RTC APB clock.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC clock Disabled

#1 : 1

RTC clock Enabled

End of enumeration elements list.

TMR0CKEN : Timer0 Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer0 clock Disabled

#1 : 1

Timer0 clock Enabled

End of enumeration elements list.

TMR1CKEN : Timer1 Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer1 clock Disabled

#1 : 1

Timer1 clock Enabled

End of enumeration elements list.

TMR2CKEN : Timer2 Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer2 clock Disabled

#1 : 1

Timer2 clock Enabled

End of enumeration elements list.

TMR3CKEN : Timer3 Clock Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer3 clock Disabled

#1 : 1

Timer3 clock Enabled

End of enumeration elements list.

CLKOCKEN : CLKO Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

CLKO clock Disabled

#1 : 1

CLKO clock Enabled

End of enumeration elements list.

I2C0CKEN : I2C0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 clock Disabled

#1 : 1

I2C0 clock Enabled

End of enumeration elements list.

I2C1CKEN : I2C1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 clock Disabled

#1 : 1

I2C1 clock Enabled

End of enumeration elements list.

SPI0CKEN : SPI0 Clock Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 clock Disabled

#1 : 1

SPI0 clock Enabled

End of enumeration elements list.

UART0CKEN : UART0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 clock Disabled

#1 : 1

UART0 clock Enabled

End of enumeration elements list.

UART1CKEN : UART1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 clock Disabled

#1 : 1

UART1 clock Enabled

End of enumeration elements list.

UART2CKEN : UART2 Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART2 clock Disabled

#1 : 1

UART2 clock Enabled

End of enumeration elements list.

UART3CKEN : UART3 Clock Enable Bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART3 clock Disabled

#1 : 1

UART3 clock Enabled

End of enumeration elements list.

UART4CKEN : UART4 Clock Enable Bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART4 clock Disabled

#1 : 1

UART4 clock Enabled

End of enumeration elements list.

USBDCKEN : USB Device Clock Enable Bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

USB Device clock Disabled

#1 : 1

USB Device clock Enabled

End of enumeration elements list.

EADCCKEN : Enhanced Analog-digital-converter (EADC) Clock Enable Bit
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

EADC clock Disabled

#1 : 1

EADC clock Enabled

End of enumeration elements list.


CLK_PMUCTL (PMUCTL)

Power Manager Control Register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PMUCTL CLK_PMUCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMSEL

PDMSEL : Power-down Mode Selection (Write Protect) This is a protected register. Please refer to open lock sequence to program it. These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Power-down mode is selected. (PD)

#010 : 2

fast wake up

#110 : 6

Deep Power-down mode is selected (DPD)

End of enumeration elements list.


CLK_HXTFSEL (HXTFSEL)

HXT Filter Select Control Register
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_HXTFSEL CLK_HXTFSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTFSEL

HXTFSEL : HXT Filter Select Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: This bit should not be changed during HXT running.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

HXT frequency is greater than 12 MHz

#1 : 1

HXT frequency is less than or equal to 12 MHz

End of enumeration elements list.


CLK_APBCLK1 (APBCLK1)

APB Devices Clock Enable Control Register 1
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_APBCLK1 CLK_APBCLK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USCI0CKEN BPWM0CKEN

USCI0CKEN : USCI0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

USCI0 clock Disabled

#1 : 1

USCI0 clock Enabled

End of enumeration elements list.

BPWM0CKEN : BPWM0 Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM0 clock Disabled

#1 : 1

BPWM0 clock Enabled

End of enumeration elements list.



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