Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0xC Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
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address_offset : 0x50 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
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address_offset : 0x80 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x90 Bytes (0x0)
size : 0x58 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xF0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
Test Register (P*)
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LBCK : Loop Back Mode
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset value, Loop Back Mode Disabled
#1 : 1
Loop Back Mode Enabled (refer to TEST Mode in the Operation Mode section)
End of enumeration elements list.
TX : Control of Transmit Pin
bits : 5 - 6 (2 bit)
access : read-only
Enumeration:
#00 : 0
Reset value, CANx_TXD controlled by the CAN Core, updated at the end of the CAN bit time
#01 : 1
Sample Point can be monitored at pin CANx_TXD
#10 : 2
Dominant ('0') level at pin CANx_TXD
#11 : 3
Recessive ('1') level at pin CANx_TXD
End of enumeration elements list.
RX : Receive Pin
Monitors the actual value of pin CANx_RXD
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
The CAN bus is dominant (CANx_RXD = 0)
#1 : 1
The CAN bus is recessive (CANx_RXD = 1)
End of enumeration elements list.
RAM Watchdog (P*)
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDC : Watchdog Configuration
Start value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled.
bits : 0 - 7 (8 bit)
access : read-only
WDV : Watchdog Value
Actual Message RAM Watchdog Counter Value.
bits : 8 - 15 (8 bit)
access : read-only
CC Control Register (Pp*)
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initialization
Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Initialization is started
End of enumeration elements list.
CCE : Configuration Change Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The CPU has no write access to the protected configuration registers
#1 : 1
The CPU has write access to the protected configuration registers (while CANFD_INIT (CANFD_CCCR[0]) = 1)
End of enumeration elements list.
ASM : Restricted Operation Mode
Bit ASM can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the software at any time. This bit will be set automatically set to 1 when the Tx handler was not able to read data from the message RAM in time. For a description of the Restricted Operation Mode refer to Restricted Operation Mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal CAN operation
#1 : 1
Restricted Operation Mode active
End of enumeration elements list.
CSA : Clock Stop Acknowledge
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No clock stop acknowledged
#1 : 1
The Controller may be set in power down by stopping AHB clock and CAN Core clock
End of enumeration elements list.
CSR : Clock Stop Request
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No clock stop is requested
#1 : 1
Clock stop requested. When clock stop is requested, rst INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle
End of enumeration elements list.
MON : Bus Monitoring Mode
Bit MON can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the Host at any time.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus Monitoring Mode Disabled
#1 : 1
Bus Monitoring Mode Enabled
End of enumeration elements list.
DAR : Disable Automatic Retransmission
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Automatic retransmission of messages not transmitted successfully Enabled
#1 : 1
Automatic retransmission Disabled
End of enumeration elements list.
TEST : Test Mode Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation, register TEST holds reset values
#1 : 1
Test Mode, write access to register TEST enabled
End of enumeration elements list.
FDOE : FD Operation Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
FD operation Disabled
#1 : 1
FD operation Enabled
End of enumeration elements list.
BRSE : Bit Rate Switch Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit rate switching for transmissions Disabled
#1 : 1
Bit rate switching for transmissions Enabled
End of enumeration elements list.
PXHD : Protocol Exception Handling Disable
Note: When protocol exception handling is disabled, the controller will transmit an error frame when it detects a protocol exception condition.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Protocol exception handling Enabled
#1 : 1
Protocol exception handling Disabled
End of enumeration elements list.
EFBI : Edge Filtering during Bus Integration
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge filtering Disabled
#1 : 1
Two consecutive dominant tq required to detect an edge f or hard synchronization
End of enumeration elements list.
TXP : Transmit Pause
If this bit is set, the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to Tx Handling section).
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit pause Disabled
#1 : 1
Transmit pause Enabled
End of enumeration elements list.
NISO : Non ISO Operation
If this bit is set, the CAN FD controller uses the CAN FD frame format as speci ed by the Bosch CAN FD Speci cation V1.0.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAN FD frame format according to ISO 11898-1:2015
#1 : 1
CAN FD frame format according to Bosch CAN FD Speci cation V1.0
End of enumeration elements list.
Nominal Bit Timing Prescaler Register (P*)
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NTSEG2 : Nominal Time Segment after Sample Point
Note: With a CAN Core clock (cclk) of 8 MHz, the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s.
bits : 0 - 6 (7 bit)
access : read-only
NTSEG1 : Nominal Time Segment before Sample Point
bits : 8 - 15 (8 bit)
access : read-only
NBRP : Nominal Bit Rate Prescaler
The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used
bits : 16 - 24 (9 bit)
access : read-only
NSJW : Nominal Re-Synchronization Jump Width
bits : 25 - 31 (7 bit)
access : read-only
Timestamp Counter Configuration (P*)
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSS : Timestamp Select
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#00 : 0
Timestamp counter value always 0x0000
#01 : 1
Timestamp counter value incremented according to TCP
#10 : 2
Reserved.
#11 : 3
Same as '00'
End of enumeration elements list.
TCP : Timestamp Counter Prescaler
Con gures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
bits : 16 - 19 (4 bit)
access : read-only
Timestamp Counter Value (C*)
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSC : Timestamp Counter
Note: A 'wrap around' is a change of the Timestamp Counter value from non-zero to 0 not caused by write access to CANFD_TSCV.
bits : 0 - 15 (16 bit)
access : read-only
Timeout Counter Configuration (P*)
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ETOC : Enable Timeout Counter
Note: For use of timeout function with CAN FD, refer to Timeout Counter section.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Timeout Counter Disabled
#1 : 1
Timeout Counter Enabled
End of enumeration elements list.
TOS : Timeout Select
When operating in Continuous mode, a write to CANFD_TOCV presets the counter to the value con gured by CANFD_TOP (TOCC[31:16]) and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value con gured by CANFD_TOP (TOCC[31:16]). Down-counting is started when the rst FIFO element is stored.
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
#00 : 0
Continuous operation
#01 : 1
Timeout controlled by Tx Event FIFO
#10 : 2
Timeout controlled by Rx FIFO 0
#11 : 3
Timeout controlled by Rx FIFO 1
End of enumeration elements list.
TOP : Timeout Period
Start value of the Timeout Counter (down-counter). Con gures the Timeout Period.
bits : 16 - 31 (16 bit)
access : read-only
Timeout Counter Value (C*)
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TOC : Timeout Counter
The filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the configuration of TCP (CANFD_TSCC[19:16]). When decremented to 0, interrupt flag TOO (CANFD_IR[18]) is set and the timeout counter is stopped. Start and reset/restart conditions are con gured via TOS (CANFD_TOCC[1:0]).
bits : 0 - 15 (16 bit)
access : read-only
Error Counter Register (X*)
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEC : Transmit Error Counter
Actual state of the Transmit Error Counter, values between 0 and 255.
Note: When ASM (CANFD_CCCR[2]) is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.
bits : 0 - 7 (8 bit)
access : read-only
REC : Receive Error Counter
Actual state of the Receive Error Counter, values between 0 and 127.
bits : 8 - 14 (7 bit)
access : read-only
RP : Receive Error Passive
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
The Receive Error Counter is below the error passive level of 128
#1 : 1
The Receive Error Counter has reached the error passive level of 128
End of enumeration elements list.
CEL : CAN Error Logging
The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC.
The counter is reset by read access to CEL. The counter stops at 0xFF the next increment of TEC or REC sets interrupt flag ELO (CANFD_IR[22]).
bits : 16 - 23 (8 bit)
access : read-only
Protocol Status Register (XS*)
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LEC : Last Error Code
The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error.
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
#000 : 0
No Error: No error occurred since LEC has been reset by successful reception or transmission
#001 : 1
Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed
#010 : 2
Form Error: A fixed format part of a received frame has the wrong format
#011 : 3
AckError: The message transmitted by the CANFD CONTROLLER was not acknowledged by another node
#100 : 4
Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant
#101 : 5
Bit0Error : During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed)
#110 : 6
CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data
#111 : 7
NoChange: Any read access to the Protocol Status Register re-initializes the LEC to 7.When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the Protocol Status Register
End of enumeration elements list.
ACT : Activity
Monitors the module's CAN communication state.
bits : 3 - 4 (2 bit)
access : read-only
Enumeration:
#00 : 0
Synchronizing - node is synchronizing on CAN communication
#01 : 1
Idle - node is neither receiver nor transmitter
#10 : 2
Receiver - node is operating as receiver
#11 : 3
Transmitter - node is operating as transmitter
End of enumeration elements list.
EP : Error Passive
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
The CAN FD controller is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected
#1 : 1
The CAN FD controller is in the Error_Passive state
End of enumeration elements list.
EW : Warning Status
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Both error counters are below the Error_Warning limit of 96
#1 : 1
At least one of error counter has reached the Error_Warning limit of 96
End of enumeration elements list.
BO : Bus_Off Status
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
The CAN FD controller is not Bus_Off
#1 : 1
The CAN FD controller is in Bus_Off state
End of enumeration elements list.
DLEC : Data Phase Last Error Code
Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to 0 when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.
bits : 8 - 10 (3 bit)
access : read-only
RESI : ESI flag of last received CAN FD Message
This bit is set together with RFDF, independent of acceptance filtering.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
Last received CAN FD message did not have its ESI flag set
#1 : 1
Last received CAN FD message had its ESI flag set
End of enumeration elements list.
RBRS : BRS flag of last received CAN FD Message
This bit is set together with RFDF, independent of acceptance filtering.
Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
Last received CAN FD message did not have its BRS flag set
#1 : 1
Last received CAN FD message had its BRS flag set
End of enumeration elements list.
RFDF : Received a CAN FD Message
This bit is set independent of acceptance filtering.
Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
Since this bit was reset by the CPU, no CAN FD message has been received
#1 : 1
Message in CAN FD format with FDF flag set has been received
End of enumeration elements list.
PXE : Protocol Exception Event
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
No protocol exception event occurred since last read access
#1 : 1
Protocol exception event occurred
End of enumeration elements list.
TDCV : Transmitter Delay Compensation Value
Position of the secondary sample point, de ned by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (TDCR[[14:8]). The SSP position is, in the data phase, the number of minimum time quata (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.
bits : 16 - 22 (7 bit)
access : read-only
Transmitter Delay Compensation Register (P*)
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TDCF : Transmitter Delay Compensation Filter Window Length
De nes the minimum value for the SSP position, dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq.
bits : 0 - 6 (7 bit)
access : read-only
TDCO : Transmitter Delay Compensation SSP Offset
Offset value de ning the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point. Valid values are 0 to 127 mtq.
bits : 8 - 14 (7 bit)
access : read-only
Interrupt Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0N : Rx FIFO 0 New Message
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No new message written to Rx FIFO 0
#1 : 1
New message written to Rx FIFO 0
End of enumeration elements list.
RF0W : Rx FIFO 0 Watermark Reached
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rx FIFO 0 ll level below watermark
#1 : 1
Rx FIFO 0 ll level reached watermark
End of enumeration elements list.
RF0F : Rx FIFO 0 Full
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rx FIFO 0 not full
#1 : 1
Rx FIFO 0 full
End of enumeration elements list.
RF0L : Rx FIFO 0 Message Lost
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Rx FIFO 0 message lost
#1 : 1
Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero
End of enumeration elements list.
RF1N : Rx FIFO 1 New Message
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No new message written to Rx FIFO 1
#1 : 1
New message written to Rx FIFO 1
End of enumeration elements list.
RF1W : Rx FIFO 1 Watermark Reached
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rx FIFO 1 ll level below watermark
#1 : 1
Rx FIFO 1 ll level reached watermark
End of enumeration elements list.
RF1F : Rx FIFO 1 Full
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rx FIFO 1 not full
#1 : 1
Rx FIFO 1 full
End of enumeration elements list.
RF1L : Rx FIFO 1 Message Lost
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Rx FIFO 1 message lost
#1 : 1
Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero
End of enumeration elements list.
HPM : High Priority Message
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No high priority message received
#1 : 1
High priority message received
End of enumeration elements list.
TC : Transmission Completed
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transmission completed
#1 : 1
Transmission completed
End of enumeration elements list.
TCF : Transmission Cancellation Finished
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transmission cancellation finished
#1 : 1
Transmission cancellation finished
End of enumeration elements list.
TFE : Tx FIFO Empty
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx FIFO non-empty
#1 : 1
Tx FIFO empty
End of enumeration elements list.
TEFN : Tx Event FIFO New Entry
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx Event FIFO unchanged
#1 : 1
Tx Handler wrote Tx Event FIFO element
End of enumeration elements list.
TEFW : Tx Event FIFO Watermark Reached
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx Event FIFO ll level below watermark
#1 : 1
Tx Event FIFO ll level reached watermark
End of enumeration elements list.
TEFF : Tx Event FIFO Full
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx Event FIFO not full
#1 : 1
Tx Event FIFO full
End of enumeration elements list.
TEFL : Tx Event FIFO Element Lost
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Tx Event FIFO element lost
#1 : 1
Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero
End of enumeration elements list.
TSW : Timestamp Wraparound
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No timestamp counter wrap-around
#1 : 1
Timestamp counter wrapped around
End of enumeration elements list.
MRAF : Message RAM Access Failure
The flag is set, when the Rx Handler
• Has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
• Was not able to write a message to the Message RAM. In this case message storage is aborted.
In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location.
The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the CAN FD controller is switched into Restricted Operation Mode (refer to Restricted Operation Mode). To leave Restricted Operation Mode, the Host CPU has to reset CANFD_ASM (CANFD_CCCR[2]).
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Message RAM access failure occurred
#1 : 1
Message RAM access failure occurred
End of enumeration elements list.
TOO : Timeout Occurred
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
No timeout
#1 : 1
Timeout reached
End of enumeration elements list.
DRX : Message stored to Dedicated Rx Buffer
The flag is set whenever a received message has been stored into a dedicated Rx Buffer.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Rx Buffer updated
#1 : 1
At least one received message stored into an Rx Buffer
End of enumeration elements list.
ELO : Error Logging Overflow
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAN Error Logging Counter did not overflow
#1 : 1
Overflow of CAN Error Logging Counter occurred
End of enumeration elements list.
EP : Error Passive
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Error_Passive status unchanged
#1 : 1
Error_Passive status changed
End of enumeration elements list.
EW : Warning Status
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Error_Warning status unchanged
#1 : 1
Error_Warning status changed
End of enumeration elements list.
BO : Bus_Off Status
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus_Off status unchanged
#1 : 1
Bus_Off status changed
End of enumeration elements list.
WDI : Watchdog Interrupt
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Message RAM Watchdog event occurred
#1 : 1
Message RAM Watchdog event due to missing READY
End of enumeration elements list.
PEA : Protocol Error in Arbitration Phase
Note: Nominal bit time is used.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No protocol error in arbitration phase
#1 : 1
Protocol error in arbitration phase detected (CANFD_LEC (CANFD_PSR[2:0]) no equal 0 or 7)
End of enumeration elements list.
PED : Protocol Error in Data Phase
Note: Data bit time is used.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No protocol error in data phase
#1 : 1
Protocol error in data phase detected (DLEC (CANFD_PSR[10:8]) no equal 0 or 7)
End of enumeration elements list.
ARA : Access to Reserved Address
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
No access to reserved address occurred
#1 : 1
Access to reserved address occurred
End of enumeration elements list.
Interrupt Enable
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NE : Rx FIFO 0 New Message Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
RF0WE : Rx FIFO 0 Watermark Reached Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
RF0FE : Rx FIFO 0 Full Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
RF0LE : Rx FIFO 0 Message Lost Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
RF1NE : Rx FIFO 1 New Message Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
RF1WE : Rx FIFO 1 Watermark Reached Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
RF1FE : Rx FIFO 1 Full Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
RF1LE : Rx FIFO 1 Message Lost Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
HPME : High Priority Message Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
TCE : Transmission Completed Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
TCFE : Transmission Cancellation Finished Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
TFEE : Tx FIFO Empty Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
TEFNE : Tx Event FIFO New Entry Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
TEFWE : Tx Event FIFO Watermark Reached Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
TEFFE : Tx Event FIFO Full Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
TEFLE : Tx Event FIFO Event Lost Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
TSWE : Timestamp Wraparound Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
MRAFE : Message RAM Access Failure Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
TOOE : Timeout Occurred Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
DRXE : Message stored to Dedicated Rx Buffer Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
BECE : Bit Error Corrected Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
BEUE : Bit Error Uncorrected Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
ELOE : Error Logging Overflow Interrupt Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
EPE : Error Passive Interrupt Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
EWE : Warning Status Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
BOE : Bus_Off Status Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
WDIE : Watchdog Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
PEAE : Protocol Error in Arbitration Phase Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
PEDE : Protocol Error in Data Phase Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
ARAE : Access to Reserved Address Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
Interrupt Line Select
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NL : Rx FIFO 0 New Message Interrupt Line
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
RF0WL : Rx FIFO 0 Watermark Reached Interrupt Line
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
RF0FL : Rx FIFO 0 Full Interrupt Line
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
RF0LL : Rx FIFO 0 Message Lost Interrupt Line
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
RF1NL : Rx FIFO 1 New Message Interrupt Line
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
RF1WL : Rx FIFO 1 Watermark Reached Interrupt Line
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
RF1FL : Rx FIFO 1 Full Interrupt Line
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
RF1LL : Rx FIFO 1 Message Lost Interrupt Line
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
HPML : High Priority Message Interrupt Line
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
TCL : Transmission Completed Interrupt Line
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
TCFL : Transmission Cancellation Finished Interrupt Line
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
TFEL : Tx FIFO Empty Interrupt Line
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
TEFNL : Tx Event FIFO New Entry Interrupt Line
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
TEFWL : Tx Event FIFO Watermark Reached Interrupt Line
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
TEFFL : Tx Event FIFO Full Interrupt Line
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
TEFLL : Tx Event FIFO Event Lost Interrupt Line
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
TSWL : Timestamp Wraparound Interrupt Line
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
MRAFL : Message RAM Access Failure Interrupt Line
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
TOOL : Timeout Occurred Interrupt Line
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
DRXL : Message stored to Dedicated Rx Buffer Interrupt Line
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
ELOL : Error Logging Overflow Interrupt Line
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
EPL : Error Passive Interrupt Line
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
EWL : Warning Status Interrupt Line
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
BOL : Bus_Off Status Interrupt Line
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
WDIL : Watchdog Interrupt Line
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
PEAL : Protocol Error in Arbitration Phase Line
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
PEDL : Protocol Error in Data Phase Line
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
ARAL : Access to Reserved Address Line
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt assigned to CAN interrupt line 0
#1 : 1
Interrupt assigned to CAN interrupt line 1
End of enumeration elements list.
Interrupt Line Enable
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENT0 : Enable Interrupt Line 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt line canfd_int0 Disabled
#1 : 1
Interrupt line canfd_int0 Enabled
End of enumeration elements list.
ENT1 : Enable Interrupt Line 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt line canfd_int1 Disabled
#1 : 1
Interrupt line canfd_int1 Enabled
End of enumeration elements list.
Global Filter Configuration (P*)
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RRFE : Reject Remote Frames Extended
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Filter remote frames with 29-bit extended IDs
#1 : 1
Reject all remote frames with 29-bit extended IDs
End of enumeration elements list.
RRFS : Reject Remote Frames Standard
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Filter remote frames with 11-bit standard IDs
#1 : 1
Reject all remote frames with 11-bit standard IDs
End of enumeration elements list.
ANFE : Accept Non-matching Frames Extended
De nes how received messages with 29-bit IDs that do not match any element of the filter list are treated.
bits : 2 - 3 (2 bit)
access : read-only
Enumeration:
#00 : 0
Accept in Rx FIFO 0
#01 : 1
Accept in Rx FIFO 1
#10 : 2
Reject
#11 : 3
Reject
End of enumeration elements list.
ANFS : Accept Non-matching Frames Standard
De nes how received messages with 11-bit IDs that do not match any element of the filter list are treated.
bits : 4 - 5 (2 bit)
access : read-only
Enumeration:
#00 : 0
Accept in Rx FIFO 0
#01 : 1
Accept in Rx FIFO 1
#10 : 2
Reject
#11 : 3
Reject
End of enumeration elements list.
Standard ID Filter Configuration (P*)
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FLSSA : Filter List Standard Start Address
Start address of standard Message ID filter list (32-bit word address, refer to Figure 6.2011).
bits : 2 - 15 (14 bit)
access : read-only
LSS : List Size Standard
bits : 16 - 23 (8 bit)
access : read-only
Enumeration:
0 : 0
No standard Message ID filter
End of enumeration elements list.
Extended ID Filter Configuration (P*)
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FLESA : Filter List Extended Start Address
Start address of extended Message ID filter list (32-bit word address, refer to Figure 6.2011).
bits : 2 - 15 (14 bit)
access : read-only
LSE : List Size Extended
bits : 16 - 22 (7 bit)
access : read-only
Enumeration:
0 : 0
No extended Message ID filter
End of enumeration elements list.
Extended ID AND Mask (P*)
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EIDM : Extended ID Mask
For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active.
bits : 0 - 28 (29 bit)
access : read-only
High Priority Message Status
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIDX : Buffer Index
bits : 0 - 5 (6 bit)
access : read-only
MSI : Message Storage Indicator
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
#00 : 0
No FIFO selected
#01 : 1
FIFO message lost
#10 : 2
Message stored in FIFO 0
#11 : 3
Message stored in FIFO 1
End of enumeration elements list.
FIDX : Filter Index
Index of matching filter element. Range is 0 to CANFD_SIDFC.LSS - 1 or CANFD_XIDFC.LSE - 1
bits : 8 - 14 (7 bit)
access : read-only
FLST : Filter List
Indicates the filter list of the matching filter element.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
Standard Filter List
#1 : 1
Extended Filter List
End of enumeration elements list.
New Data 1
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDn : New Data
The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
Rx Buffer not updated
1 : 1
Rx Buffer updated from new message
End of enumeration elements list.
New Data 2
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDn : New Data
The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
Rx Buffer not updated
1 : 1
Rx Buffer updated from new message
End of enumeration elements list.
Rx FIFO 0 Configuration (P*)
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F0SA : Rx FIFO 0 Start Address
Start address of Rx FIFO 0 in Message RAM (32-bit word address).
bits : 2 - 15 (14 bit)
access : read-only
F0S : Rx FIFO 0 Size
The Rx FIFO 0 elements are indexed from 0 to F0S-1
bits : 16 - 22 (7 bit)
access : read-only
Enumeration:
0 : 0
No Rx FIFO 0
End of enumeration elements list.
F0WM : Rx FIFO 0 Watermark
bits : 24 - 30 (7 bit)
access : read-only
Enumeration:
0 : 0
Watermark interrupt Disabled
End of enumeration elements list.
F0OM : FIFO 0 Operation Mode
FIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs).
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
FIFO 0 blocking mode
#1 : 1
FIFO 0 overwrite mode
End of enumeration elements list.
Rx FIFO 0 Status
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F0FL : Rx FIFO 0 Fill Level
Number of elements stored in Rx FIFO 0, range 0 to 64
bits : 0 - 6 (7 bit)
access : read-only
F0GI : Rx FIFO 0 Get Index
Rx FIFO 0 read index pointer, range 0 to 63.
bits : 8 - 13 (6 bit)
access : read-only
F0PI : Rx FIFO 0 Put Index
Rx FIFO 0 write index pointer, range 0 to 63.
bits : 16 - 21 (6 bit)
access : read-only
F0F : Rx FIFO 0 Full
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
Rx FIFO 0 not full
#1 : 1
Rx FIFO 0 full
End of enumeration elements list.
RF0L : Rx FIFO 0 Message Lost
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#1 : 1
Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero
End of enumeration elements list.
Rx FIFO 0 Acknowledge
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0A : Rx FIFO 0 Acknowledge Index
After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]) to F0AI (CANFD_RXF0A[5:0]) + 1 and update the FIFO 0 Fill Level CANFD_RXF0S.F0FL.
bits : 0 - 5 (6 bit)
access : read-write
Rx Buffer Configuration (P*)
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RBSA : Rx Buffer Start Address
Con gures the start address of the Rx Buffers section in the Message RAM (32-bit word address).
bits : 2 - 15 (14 bit)
access : read-only
Rx FIFO 1 Configuration (P*)
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F1SA : Rx FIFO 1 Start Address
Start address of Rx FIFO 1 in Message RAM (32-bit word address, refer to Figure 6.2011).
bits : 2 - 15 (14 bit)
access : read-only
F1S : Rx FIFO 1 Size
The Rx FIFO 1 elements are indexed from 0 to F1S - 1
bits : 16 - 22 (7 bit)
access : read-only
Enumeration:
0 : 0
No Rx FIFO 1
End of enumeration elements list.
F1WM : Rx FIFO 1 Watermark
bits : 24 - 30 (7 bit)
access : read-only
Enumeration:
0 : 0
Watermark interrupt Disabled
End of enumeration elements list.
F1OM : FIFO 1 Operation Mode
FIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs).
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
FIFO 1 blocking mode
#1 : 1
FIFO 1 overwrite mode
End of enumeration elements list.
Rx FIFO 1 Status
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F1FL : Rx FIFO 1 Fill Level
Number of elements stored in Rx FIFO 1, range 0 to 64
bits : 0 - 6 (7 bit)
access : read-only
F1G : Rx FIFO 1 Get Index
Rx FIFO 1 read index pointer, range 0 to 63.
bits : 8 - 13 (6 bit)
access : read-only
F1P : Rx FIFO 1 Fill Level
Number of elements stored in Rx FIFO 1, range 0 to 64.
bits : 16 - 21 (6 bit)
access : read-only
F1F : Rx FIFO 1 Full
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
Rx FIFO 1 not full
#1 : 1
Rx FIFO 1 full
End of enumeration elements list.
RF1L : Rx FIFO 1 Message Lost
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#1 : 1
Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero
End of enumeration elements list.
Rx FIFO 1 Acknowledge
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1A : Rx FIFO 1 Acknowledge Index
After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]) to F1AI (CANFD_RXF1A[5:0]) + 1 and update the FIFO 1 Fill Level F1FL (CANFD_RXF1S[6:0]).
bits : 0 - 5 (6 bit)
access : read-write
Rx Buffer / FIFO Element Size Configuration (P*)
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F0DS : Rx FIFO 0 Data Field Size
Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame data field is ignored.
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
#000 : 0
8 byte data field
#001 : 1
12 byte data field
#010 : 2
16 byte data field
#011 : 3
20 byte data field
#100 : 4
24 byte data field
#101 : 5
32 byte data field
#110 : 6
48 byte data field
#111 : 7
64 byte data field
End of enumeration elements list.
F1DS : Rx FIFO 1 Data Field Size
bits : 4 - 6 (3 bit)
access : read-only
Enumeration:
#000 : 0
8 byte data field
#001 : 1
12 byte data field
#010 : 2
16 byte data field
#011 : 3
20 byte data field
#100 : 4
24 byte data field
#101 : 5
32 byte data field
#110 : 6
48 byte data field
#111 : 7
64 byte data field
End of enumeration elements list.
RBDS : Rx Buffer Data Field Size
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
#000 : 0
8 byte data field
#001 : 1
12 byte data field
#010 : 2
16 byte data field
#011 : 3
20 byte data field
#100 : 4
24 byte data field
#101 : 5
32 byte data field
#110 : 6
48 byte data field
#111 : 7
64 byte data field
End of enumeration elements list.
Data Bit Timing Prescaler Register (P*)
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DSJW : Data Re-Synchronization Jump Width
bits : 0 - 3 (4 bit)
access : read-only
DTSEG2 : Data time segment after sample point
bits : 4 - 7 (4 bit)
access : read-only
DTSEG1 : Data time segment before sample point
bits : 8 - 12 (5 bit)
access : read-only
DBRP : Data Bit Rate Prescaler
bits : 16 - 20 (5 bit)
access : read-only
TDC : Transmitter Delay Compensation
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmitter Delay Compensation Disabled
#1 : 1
Transmitter Delay Compensation Enabled
End of enumeration elements list.
Tx Buffer Configuration (P*)
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TBSA : Tx Buffers Start Address
Start address of Tx Buffers section in Message RAM (32-bit word address, refer to Figure 6.2011).
Note: The sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers.
bits : 2 - 15 (14 bit)
access : read-only
NDTB : Number of Dedicated Transmit Buffers
bits : 16 - 21 (6 bit)
access : read-only
Enumeration:
0 : 0
No Dedicated Tx Buffers
End of enumeration elements list.
TFQS : Transmit FIFO/Queue Size
bits : 24 - 29 (6 bit)
access : read-only
Enumeration:
0 : 0
No Tx FIFO/Queue
End of enumeration elements list.
TFQM : Tx FIFO/Queue Mode
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
Tx FIFO operation
#1 : 1
Tx Queue operation
End of enumeration elements list.
Tx FIFO/Queue Status
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFFL : Tx FIFO Free Level
Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.
Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.
bits : 0 - 5 (6 bit)
access : read-only
TFG : Tx FIFO Get Index
bits : 8 - 12 (5 bit)
access : read-only
TFQP : Tx FIFO/Queue Put Index
Tx FIFO/Queue write index pointer, range 0 to 31.
bits : 16 - 20 (5 bit)
access : read-only
TFQF : Tx FIFO/Queue Full
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
#0 : 0
Tx FIFO/Queue not full
#1 : 1
Tx FIFO/Queue full
End of enumeration elements list.
Tx Buffer Element Size Configuration (P*)
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TBDS : Tx Buffer Data Field Size
Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size CANFD_TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as 0xCC (padding bytes).
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
#000 : 0
8 byte data field
#001 : 1
12 byte data field
#010 : 2
16 byte data field
#011 : 3
20 byte data field
#100 : 4
24 byte data field
#101 : 5
32 byte data field
#110 : 6
48 byte data field
#111 : 7
64 byte data field
End of enumeration elements list.
Tx Buffer Request Pending
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TRPn : Transmission Request PendingEach Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register CANFD_TXBCR.
CANFD_TXBRP bits are set only for those Tx Buffers con gured via CANFD_TXBC. After a CANFD_TXBRP bit has been set, a Tx scan (refer to Tx Handling section) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID).
A cancellation request resets the corresponding transmission request pending bit of register CANFD_TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding CANFD_TXBRP bit has been reset.
After a cancellation has been requested, a finished cancellation is signaled via CANFD_TXBCF
• after successful transmission together with the corresponding CANFD_TXBTO bit
• when the transmission has not yet been started at the point of cancellation
• when the transmission has been aborted due to lost arbitration
• when an error occurred during frame transmission
In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding CANFD_TXBCF bit is set for all unsuccessful transmissions.
Note: CANFD_TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding CANFD_TXBRP bit is reset.
bits : 0 - 31 (32 bit)
access : read-only
Enumeration:
0 : 0
No transmission request pending
1 : 1
Transmission request pending
End of enumeration elements list.
Tx Buffer Add Request
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARn : Add RequestEach Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR CANFD_TXBAR bits are set only for those Tx Buffers con gured via CANFD_TXBC When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed.
Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding CANFD_TXBRP bit already set), this add request is ignored.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No transmission request added
1 : 1
Transmission requested added
End of enumeration elements list.
Tx Buffer Cancellation Request
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRn : Cancellation Request
Each Tx Buffer has its own Cancellation Request bit. Writing a 1 will set the corresponding Cancellation Request bit writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to CANFD_TXBCR. CANFD_TXBCR bits are set only for those Tx Buffers con gured via CANFD_TXBC. The bits remain set until the corresponding bit of CANFD_TXBRP is reset.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No cancellation pending
1 : 1
Cancellation pending
End of enumeration elements list.
Tx Buffer Transmission Occurred
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TOn : Transmission Occurred
Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register CANFD_TXBAR.
bits : 0 - 31 (32 bit)
access : read-only
Enumeration:
0 : 0
No transmission occurred
1 : 1
Transmission occurred
End of enumeration elements list.
Tx Buffer Cancellation Finished
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFn : Cancellation Finished
Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR. In case the corresponding CANFD_TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register CANFD_TXBAR.
bits : 0 - 31 (32 bit)
access : read-only
Enumeration:
0 : 0
No transmit buffer cancellation
1 : 1
Transmit buffer cancellation finished
End of enumeration elements list.
Tx Buffer Transmission Interrupt Enable
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIEn : Transmission Interrupt Enable
Each Tx Buffer has its own Transmission Interrupt Enable bit.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
Transmission interrupt Disabled
1 : 1
Transmission interrupt Enabled
End of enumeration elements list.
Tx Buffer Cancellation Finished Interrupt Enable
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFIEn : Cancellation Finished Interrupt Enable
Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
Cancellation finished interrupt Disabled
1 : 1
Cancellation finished interrupt Enabled
End of enumeration elements list.
Tx Event FIFO Configuration (P*)
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EFSA : Event FIFO Start Address
Start address of Tx Event FIFO in Message RAM (32-bit word address, refer to Figure 6.2011).
bits : 2 - 15 (14 bit)
access : read-only
EFS : Event FIFO Size
The Tx Event FIFO elements are indexed from 0 to EFS - 1
bits : 16 - 21 (6 bit)
access : read-only
Enumeration:
0 : 0
Tx Event FIFO Disabled
End of enumeration elements list.
EFWN : Event FIFO Watermark
bits : 24 - 29 (6 bit)
access : read-only
Enumeration:
0 : 0
Watermark interrupt Disabled
End of enumeration elements list.
Tx Event FIFO Status
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EFFL : Event FIFO Fill Level
Number of elements stored in Tx Event FIFO, range 0 to 32
bits : 0 - 5 (6 bit)
access : read-only
EFG : Event FIFO Get Index
Tx Event FIFO read index pointer, range 0 to 31
bits : 8 - 12 (5 bit)
access : read-only
EFP : Event FIFO Put Index
Tx Event FIFO write index pointer, range 0 to 31
bits : 16 - 20 (5 bit)
access : read-only
EFF : Event FIFO Full
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
Tx Event FIFO not full
#1 : 1
Tx Event FIFO full
End of enumeration elements list.
TEFL : Tx Event FIFO Element Lost
This bit is a copy of interrupt flag TEFL (CANFD_IR[15]). When TEFL is reset, this bit is also reset.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Tx Event FIFO element lost
#1 : 1
Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero
End of enumeration elements list.
Tx Event FIFO Acknowledge
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFA : Event FIFO Acknowledge Index
After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index EFGI (CANFD_TXEFS[12:8]) to EFAI + 1 and update the Event FIFO Fill Level EFFL (CANFD_TXEFS[5:0])
bits : 0 - 4 (5 bit)
access : read-write
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