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SYS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x18 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x30 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x80 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xB0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

address_offset : 0xD0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xF0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1EC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1F8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x400 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

SYS_PDID (PDID)

SYS_IPRST2 (IPRST2)

SYS_REGLCTL (REGLCTL)

SYS_BODCTL (BODCTL)

SYS_IVSCTL (IVSCTL)

SYS_PORDISAN (PORDISAN)

SYS_PLCTL (PLCTL)

SYS_PLSTS (PLSTS)

SYS_VREFCTL (VREFCTL)

SYS_GPA_MFPL (GPA_MFPL)

SYS_GPA_MFPH (GPA_MFPH)

SYS_GPB_MFPL (GPB_MFPL)

SYS_GPB_MFPH (GPB_MFPH)

SYS_RSTSTS (RSTSTS)

SYS_GPC_MFPL (GPC_MFPL)

SYS_AHBMCTL (AHBMCTL)

SYS_GPC_MFPH (GPC_MFPH)

SYS_GPD_MFPL (GPD_MFPL)

SYS_GPD_MFPH (GPD_MFPH)

SYS_GPE_MFPL (GPE_MFPL)

SYS_GPE_MFPH (GPE_MFPH)

SYS_GPF_MFPL (GPF_MFPL)

SYS_GPF_MFPH (GPF_MFPH)

SYS_GPG_MFPL (GPG_MFPL)

SYS_GPG_MFPH (GPG_MFPH)

SYS_GPH_MFPL (GPH_MFPL)

SYS_GPH_MFPH (GPH_MFPH)

SYS_GPI_MFPL (GPI_MFPL)

SYS_IPRST0 (IPRST0)

SYS_GPA_MFOS (GPA_MFOS)

SYS_GPB_MFOS (GPB_MFOS)

SYS_GPC_MFOS (GPC_MFOS)

SYS_GPD_MFOS (GPD_MFOS)

SYS_GPE_MFOS (GPE_MFOS)

SYS_GPF_MFOS (GPF_MFOS)

SYS_GPG_MFOS (GPG_MFOS)

SYS_GPH_MFOS (GPH_MFOS)

SYS_GPI_MFOS (GPI_MFOS)

SYS_MODCTL (MODCTL)

SYS_IPRST1 (IPRST1)

SYS_SRAM_INTCTL (SRAM_INTCTL)

SYS_SRAM_STATUS (SRAM_STATUS)

SYS_SRAM_ERRADDR (SRAM_ERRADDR)

SYS_SRAM_BISTCTL (SRAM_BISTCTL)

SYS_SRAM_BISTSTS (SRAM_BISTSTS)

SYS_IRCTCTL (IRCTCTL)

SYS_IRCTIEN (IRCTIEN)

SYS_IRCTISTS (IRCTISTS)


SYS_PDID (PDID)

Part Device Identification Number Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYS_PDID SYS_PDID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDID

PDID : Part Device Identification Number (Read Only) This register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only


SYS_IPRST2 (IPRST2)

Peripheral Reset Control Register 2
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IPRST2 SYS_IPRST2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACRST CIR0RST EPWM0RST EPWM1RST BPWM0RST BPWM1RST PRNGRST

DACRST : DAC Controller Reset
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC controller normal operation

#1 : 1

DAC controller reset

End of enumeration elements list.

CIR0RST : CIR0 Controller Reset
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

CIR0 controller normal operation

#1 : 1

CIR0 controller reset

End of enumeration elements list.

EPWM0RST : EPWM0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

EPWM0 controller normal operation

#1 : 1

EPWM0 controller reset

End of enumeration elements list.

EPWM1RST : EPWM1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

EPWM1 controller normal operation

#1 : 1

EPWM1 controller reset

End of enumeration elements list.

BPWM0RST : BPWM0 Controller Reset
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM0 controller normal operation

#1 : 1

BPWM0 controller reset

End of enumeration elements list.

BPWM1RST : BPWM1 Controller Reset
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM1 controller normal operation

#1 : 1

BPWM1 controller reset

End of enumeration elements list.

PRNGRST : PRNG Controller Reset
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

PRNG controller normal operation

#1 : 1

PRNG controller reset

End of enumeration elements list.


SYS_REGLCTL (REGLCTL)

Register Lock Control Register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_REGLCTL SYS_REGLCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGLCTL

REGLCTL : Register Lock Control Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. REGLCTL[0] Register Lock Control Disable Index (Read Only)
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : 0

Write-protection Enabled for writing protected registers. Any write to the protected register is ignored

1 : 1

Write-protection Disabled for writing protected registers

End of enumeration elements list.


SYS_BODCTL (BODCTL)

Brown-out Detector Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_BODCTL SYS_BODCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODEN BODRSTEN BODIF BODLPM BODOUT LVREN BODDGSEL LVRDGSEL BODVL

BODEN : Brown-out Detector Enable Bit (Write Protect) The default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]). Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brown-out Detector function Disabled

#1 : 1

Brown-out Detector function Enabled

End of enumeration elements list.

BODRSTEN : Brown-out Reset Enable Bit (Write Protect) The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit. Note 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will be kept till to the BODEN is set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brown-out 'INTERRUPT' function Enabled

#1 : 1

Brown-out 'RESET' function Enabled

End of enumeration elements list.

BODIF : Brown-out Detector Interrupt Flag Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting

#1 : 1

When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled

End of enumeration elements list.

BODLPM : Brown-out Detector Low Power Mode (Write Protect) Note 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. Note 3:BOD enable stable time is 50us, period enable time need larger than it
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

BOD operate in normal mode (default)

#1 : 1

BOD Low Power mode Enabled

End of enumeration elements list.

BODOUT : Brown-out Detector Output Status It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brown-out Detector output status is 0

#1 : 1

Brown-out Detector output status is 1

End of enumeration elements list.

LVREN : Low Voltage Reset Enable Bit (Write Protect) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. Note 1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Low Voltage Reset function Disabled

#1 : 1

Low Voltage Reset function Enabled

End of enumeration elements list.

BODDGSEL : Brown-out Detector Output De-glitch Time Select (Write Protect) Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

BOD output is sampled by RC10K clock

#001 : 1

4 system clock (HCLK)

#010 : 2

8 system clock (HCLK)

#011 : 3

16 system clock (HCLK)

#100 : 4

32 system clock (HCLK)

#101 : 5

64 system clock (HCLK)

#110 : 6

128 system clock (HCLK)

#111 : 7

256 system clock (HCLK)

End of enumeration elements list.

LVRDGSEL : LVR Output De-glitch Time Select (Write Protect) Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

Without de-glitch function

#001 : 1

4 system clock (HCLK)

#010 : 2

8 system clock (HCLK)

#011 : 3

16 system clock (HCLK)

#100 : 4

32 system clock (HCLK)

#101 : 5

64 system clock (HCLK)

#110 : 6

128 system clock (HCLK)

#111 : 7

256 system clock (HCLK)

End of enumeration elements list.

BODVL : Brown-out Detector Threshold Voltage Selection (Write Protect) The default value is set by Flash controller user configuration register CBOV (CONFIG0 [22:21]). Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

Brown-Out Detector threshold voltage is 2.4V

#01 : 1

Brown-Out Detector threshold voltage is 2.7V

#10 : 2

Brown-Out Detector threshold voltage is 3.7V

#11 : 3

Brown-Out Detector threshold voltage is 4.4V

End of enumeration elements list.


SYS_IVSCTL (IVSCTL)

Internal Voltage Source Control Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IVSCTL SYS_IVSCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VTEMPEN

VTEMPEN : Temperature Sensor Enable Bit This bit is used to enable/disable temperature sensor function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Temperature sensor function Disabled (default)

#1 : 1

Temperature sensor function Enabled

End of enumeration elements list.


SYS_PORDISAN (PORDISAN)

Analog POR Disable Control Register
address_offset : 0x1EC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_PORDISAN SYS_PORDISAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POROFFAN

POROFFAN : Power-on Reset Enable Bit (Write Protect) After powered on, user can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field. The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write


SYS_PLCTL (PLCTL)

Power Level Control Register
address_offset : 0x1F8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_PLCTL SYS_PLCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSEL LVSSTEP LVSPRD

PLSEL : Power Level Select(Write Protect) These bits indicate the status of power level. Note: Refer to section 6.2.5 for Power Modes and Power Level Transition.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Power level is PL0

#01 : 1

Power level is PL1

End of enumeration elements list.

LVSSTEP : LDO Voltage Scaling Step(Write Protect) The LVSSTEP value is LDO voltage rising step.
bits : 16 - 20 (5 bit)
access : read-write

LVSPRD : LDO Voltage Scaling Period(Write Protect) The LVSPRD value is the period of each LDO voltage rising step.
bits : 24 - 31 (8 bit)
access : read-write


SYS_PLSTS (PLSTS)

Power Level Status Register
address_offset : 0x1FC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYS_PLSTS SYS_PLSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLCBUSY PLSTATUS

PLCBUSY : Power Level Change Busy Bit (Read Only) This bit is set by hardware when power level is changing. After power level change is completed, this bit will be cleared automatically by hardware.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Core voltage change is completed

#1 : 1

Core voltage change is ongoing

End of enumeration elements list.

PLSTATUS : Power Level Status (Read Only) This bit indicates the status of power level.
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

#00 : 0

Power level is PL0

#01 : 1

Power level is PL1

End of enumeration elements list.


SYS_VREFCTL (VREFCTL)

VREF Control Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_VREFCTL SYS_VREFCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREFCTL PRELOADEN VBGFEN

VREFCTL : VREF Control Bits (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

#00000 : 0

VREF is from external pin

#00010 : 2

VREF is from internal reference voltage 2.048V

#00110 : 6

VREF is from internal reference voltage 2.56V

#01010 : 10

VREF is from internal reference voltage 3.072V

#01110 : 14

VREF is from internal reference voltage 4.096V

End of enumeration elements list.

PRELOADEN : Pre-load Function Enable Bit (Write Protect) This bit should be enabled and keep during Tstable when VREFCTL(SYS_VREFCTL[4:0]) change setting(except set to 00000). Tstable depends on different situations has different requirement, please refer to Datasheet. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

VREF Pre-load function Disabled. (Default)

#1 : 1

VREF Pre-load function Enabled

End of enumeration elements list.

VBGFEN : Chip Internal Voltage Band-gap Force Enable Bit(Write Only) Note: If user want to read the value of this bit, please read bit[25].
bits : 24 - 24 (1 bit)
access : write-only

Enumeration:

#0 : 0

Chip internal voltage band-gap controlled by ADC/ACMP if source selected

#1 : 1

Chip internal voltage band-gap force enable

End of enumeration elements list.


SYS_GPA_MFPL (GPA_MFPL)

GPIOA Low Byte Multiple Function Control Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPA_MFPL SYS_GPA_MFPL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA0MFP PA1MFP PA2MFP PA3MFP PA4MFP PA5MFP PA6MFP PA7MFP

PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PA1MFP : PA.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PA2MFP : PA.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PA3MFP : PA.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PA4MFP : PA.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PA5MFP : PA.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PA6MFP : PA.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PA7MFP : PA.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write


SYS_GPA_MFPH (GPA_MFPH)

GPIOA High Byte Multiple Function Control Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPA_MFPH SYS_GPA_MFPH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA8MFP PA9MFP PA10MFP PA11MFP PA12MFP PA13MFP PA14MFP PA15MFP

PA8MFP : PA.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PA9MFP : PA.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PA10MFP : PA.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PA11MFP : PA.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PA12MFP : PA.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PA13MFP : PA.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PA14MFP : PA.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PA15MFP : PA.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write


SYS_GPB_MFPL (GPB_MFPL)

GPIOB Low Byte Multiple Function Control Register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPB_MFPL SYS_GPB_MFPL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PB0MFP PB1MFP PB2MFP PB3MFP PB4MFP PB5MFP PB6MFP PB7MFP

PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write


SYS_GPB_MFPH (GPB_MFPH)

GPIOB High Byte Multiple Function Control Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPB_MFPH SYS_GPB_MFPH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PB8MFP PB9MFP PB10MFP PB11MFP PB12MFP PB13MFP PB14MFP PB15MFP

PB8MFP : PB.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PB9MFP : PB.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PB10MFP : PB.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PB11MFP : PB.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PB12MFP : PB.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PB13MFP : PB.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PB14MFP : PB.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PB15MFP : PB.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write


SYS_RSTSTS (RSTSTS)

System Reset Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_RSTSTS SYS_RSTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORF PINRF WDTRF LVRF BODRF SYSRF HRESETRF CPURF CPULKRF

PORF : POR Reset Flag The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from POR or CHIPRST

#1 : 1

Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system

End of enumeration elements list.

PINRF : NRESET Pin Reset Flag The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from nRESET pin

#1 : 1

Pin nRESET had issued the reset signal to reset the system

End of enumeration elements list.

WDTRF : WDT Reset Flag The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. Note 1: Write 1 to clear this bit to 0. Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from watchdog timer or window watchdog timer

#1 : 1

The watchdog timer or window watchdog timer had issued the reset signal to reset the system

End of enumeration elements list.

LVRF : LVR Reset Flag The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from LVR

#1 : 1

LVR controller had issued the reset signal to reset the system

End of enumeration elements list.

BODRF : BOD Reset Flag The BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from BOD

#1 : 1

The BOD had issued the reset signal to reset the system

End of enumeration elements list.

SYSRF : System Reset Flag The system reset flag is set by the 'Reset Signal' from the Cortex-M4 Core to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from Cortex-M4

#1 : 1

The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core

End of enumeration elements list.

HRESETRF : HRESET Reset Flag The HRESET reset flag is set by the 'Reset Signal' from the HRESET. Note: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from HRESET

#1 : 1

Reset from HRESET

End of enumeration elements list.

CPURF : CPU Reset Flag The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC). Note: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from CPU

#1 : 1

The Cortex-M4 Core and FMC are reset by software setting CPURST to 1

End of enumeration elements list.

CPULKRF : CPU Lockup Reset Flag Note 1: Write 1 to clear this bit to 0. Note 2: When CPU lockup happened under ICE is connected, this flag will set to 1 but chip will not reset.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from CPU lockup happened

#1 : 1

The Cortex-M4 lockup happened and chip is reset

End of enumeration elements list.


SYS_GPC_MFPL (GPC_MFPL)

GPIOC Low Byte Multiple Function Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPC_MFPL SYS_GPC_MFPL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC0MFP PC1MFP PC2MFP PC3MFP PC4MFP PC5MFP PC6MFP PC7MFP

PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PC1MFP : PC.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PC2MFP : PC.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PC3MFP : PC.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PC4MFP : PC.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PC5MFP : PC.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PC6MFP : PC.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PC7MFP : PC.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write


SYS_AHBMCTL (AHBMCTL)

AHB Bus Matrix Priority Control Register
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_AHBMCTL SYS_AHBMCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTACTEN

INTACTEN : Highest AHB Bus Priority of Cortex-M4 Core Enable Bit (Write Protect) Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Round-robin mode

#1 : 1

Cortex-M4 CPU with highest bus priority when interrupt occurred

End of enumeration elements list.


SYS_GPC_MFPH (GPC_MFPH)

GPIOC High Byte Multiple Function Control Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPC_MFPH SYS_GPC_MFPH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC8MFP PC9MFP PC10MFP PC11MFP PC12MFP PC13MFP PC14MFP

PC8MFP : PC.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PC9MFP : PC.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PC10MFP : PC.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PC11MFP : PC.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PC12MFP : PC.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PC13MFP : PC.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PC14MFP : PC.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write


SYS_GPD_MFPL (GPD_MFPL)

GPIOD Low Byte Multiple Function Control Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPD_MFPL SYS_GPD_MFPL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0MFP PD1MFP PD2MFP PD3MFP PD4MFP PD5MFP PD6MFP PD7MFP

PD0MFP : PD.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PD1MFP : PD.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PD2MFP : PD.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PD3MFP : PD.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PD4MFP : PD.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PD5MFP : PD.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PD6MFP : PD.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PD7MFP : PD.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write


SYS_GPD_MFPH (GPD_MFPH)

GPIOD High Byte Multiple Function Control Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPD_MFPH SYS_GPD_MFPH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD8MFP PD9MFP PD10MFP PD11MFP PD12MFP PD13MFP PD14MFP PD15MFP

PD8MFP : PD.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PD9MFP : PD.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PD10MFP : PD.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PD11MFP : PD.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PD12MFP : PD.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PD13MFP : PD.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PD14MFP : PD.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PD15MFP : PD.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write


SYS_GPE_MFPL (GPE_MFPL)

GPIOE Low Byte Multiple Function Control Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPE_MFPL SYS_GPE_MFPL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE0MFP PE1MFP PE2MFP PE3MFP PE4MFP PE5MFP PE6MFP PE7MFP

PE0MFP : PE.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PE1MFP : PE.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PE2MFP : PE.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PE3MFP : PE.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PE4MFP : PE.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PE5MFP : PE.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PE6MFP : PE.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PE7MFP : PE.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write


SYS_GPE_MFPH (GPE_MFPH)

GPIOE High Byte Multiple Function Control Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPE_MFPH SYS_GPE_MFPH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE8MFP PE9MFP PE10MFP PE11MFP PE12MFP PE13MFP PE14MFP PE15MFP

PE8MFP : PE.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PE9MFP : PE.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PE10MFP : PE.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PE11MFP : PE.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PE12MFP : PE.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PE13MFP : PE.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PE14MFP : PE.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PE15MFP : PE.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write


SYS_GPF_MFPL (GPF_MFPL)

GPIOF Low Byte Multiple Function Control Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPF_MFPL SYS_GPF_MFPL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PF0MFP PF1MFP PF2MFP PF3MFP PF4MFP PF5MFP PF6MFP PF7MFP

PF0MFP : PF.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PF1MFP : PF.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PF2MFP : PF.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PF3MFP : PF.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PF4MFP : PF.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PF5MFP : PF.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PF6MFP : PF.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PF7MFP : PF.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write


SYS_GPF_MFPH (GPF_MFPH)

GPIOF High Byte Multiple Function Control Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPF_MFPH SYS_GPF_MFPH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PF8MFP PF9MFP PF10MFP PF11MFP PF12MFP PF13MFP PF14MFP PF15MFP

PF8MFP : PF.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PF9MFP : PF.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PF10MFP : PF.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PF11MFP : PF.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PF12MFP : PF.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PF13MFP : PF.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PF14MFP : PF.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PF15MFP : PF.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write


SYS_GPG_MFPL (GPG_MFPL)

GPIOG Low Byte Multiple Function Control Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPG_MFPL SYS_GPG_MFPL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG2MFP PG3MFP PG4MFP

PG2MFP : PG.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PG3MFP : PG.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PG4MFP : PG.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write


SYS_GPG_MFPH (GPG_MFPH)

GPIOG High Byte Multiple Function Control Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPG_MFPH SYS_GPG_MFPH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG8MFP PG9MFP PG10MFP PG11MFP PG12MFP PG13MFP PG14MFP PG15MFP

PG8MFP : PG.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PG9MFP : PG.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PG10MFP : PG.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PG11MFP : PG.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PG12MFP : PG.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PG13MFP : PG.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PG14MFP : PG.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PG15MFP : PG.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write


SYS_GPH_MFPL (GPH_MFPL)

GPIOH Low Byte Multiple Function Control Register
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPH_MFPL SYS_GPH_MFPL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PH4MFP PH5MFP PH6MFP PH7MFP

PH4MFP : PH.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PH5MFP : PH.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PH6MFP : PH.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PH7MFP : PH.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write


SYS_GPH_MFPH (GPH_MFPH)

GPIOH High Byte Multiple Function Control Register
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPH_MFPH SYS_GPH_MFPH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PH8MFP PH9MFP PH10MFP PH11MFP

PH8MFP : PH.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PH9MFP : PH.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PH10MFP : PH.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PH11MFP : PH.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write


SYS_GPI_MFPL (GPI_MFPL)

GPIOI Low Byte Multiple Function Control Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPI_MFPL SYS_GPI_MFPL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PI0MFP PI1MFP PI2MFP PI3MFP PI4MFP PI5MFP

PI0MFP : PI.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PI1MFP : PI.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PI2MFP : PI.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PI3MFP : PI.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PI4MFP : PI.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PI5MFP : PI.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write


SYS_IPRST0 (IPRST0)

Peripheral Reset Control Register 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IPRST0 SYS_IPRST0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIPRST CPURST PDMARST CRCRST

CHIPRST : Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload. About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 7.2.2 Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip normal operation

#1 : 1

Chip one-shot reset

End of enumeration elements list.

CPURST : Processor Core One-shot Reset (Write Protect) Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Processor core normal operation

#1 : 1

Processor core one-shot reset

End of enumeration elements list.

PDMARST : PDMA Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA controller normal operation

#1 : 1

PDMA controller reset

End of enumeration elements list.

CRCRST : CRC Calculation Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRC calculation controller normal operation

#1 : 1

CRC calculation controller reset

End of enumeration elements list.


SYS_GPA_MFOS (GPA_MFOS)

GPIOA Multiple Function Output Select Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPA_MFOS SYS_GPA_MFOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFOS0 MFOS1 MFOS2 MFOS3 MFOS4 MFOS5 MFOS6 MFOS7 MFOS8 MFOS9 MFOS10 MFOS11 MFOS12 MFOS13 MFOS14 MFOS15

MFOS0 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS1 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS2 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS3 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS4 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS5 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS6 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS7 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS8 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS9 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS10 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS11 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS12 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS13 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS14 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.

MFOS15 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin The PC15/PG0/PG1/PG5/PG6/PG7/PG8/PH0/PH1/PH2/PH3/PH12/PH13/PH14/PH15 pins are not available.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Multiple function pin output mode type is Push-pull mode

#1 : 1

Multiple function pin output mode type is Open-drain mode

End of enumeration elements list.


SYS_GPB_MFOS (GPB_MFOS)

GPIOB Multiple Function Output Select Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPB_MFOS SYS_GPB_MFOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_GPC_MFOS (GPC_MFOS)

GPIOC Multiple Function Output Select Register
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPC_MFOS SYS_GPC_MFOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_GPD_MFOS (GPD_MFOS)

GPIOD Multiple Function Output Select Register
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPD_MFOS SYS_GPD_MFOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_GPE_MFOS (GPE_MFOS)

GPIOE Multiple Function Output Select Register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPE_MFOS SYS_GPE_MFOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_GPF_MFOS (GPF_MFOS)

GPIOF Multiple Function Output Select Register
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPF_MFOS SYS_GPF_MFOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_GPG_MFOS (GPG_MFOS)

GPIOG Multiple Function Output Select Register
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPG_MFOS SYS_GPG_MFOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_GPH_MFOS (GPH_MFOS)

GPIOH Multiple Function Output Select Register
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPH_MFOS SYS_GPH_MFOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_GPI_MFOS (GPI_MFOS)

GPIOI Multiple Function Output Select Register
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPI_MFOS SYS_GPI_MFOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYS_MODCTL (MODCTL)

Modulation Control Register
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_MODCTL SYS_MODCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODEN MODH MODPWMSEL

MODEN : Modulation Function Enable Bit This bit enables modulation funcion by modulating with EPWM0 channel output and UART0(UART0_TXD) output.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Modulation Function Disabled

#1 : 1

Modulation Function Enabled

End of enumeration elements list.

MODH : Modulation at Data High Select modulation pulse(EPWM0) at high or low of UART0_TXD. 0: Modulation pulse at UART0_TXD low. 1: Modulation pulse at UART0_TXD high.
bits : 1 - 1 (1 bit)
access : read-write

MODPWMSEL : EPWM0 Channel Select for Modulation Select the EPWM0 channel to modulate with the UART0_TXD. 0000: EPWM0 Channel 0 modulate with UART0_TXD. 0001: EPWM0 Channel 1 modulate with UART0_TXD. 0010: EPWM0 Channel 2 modulate with UART0_TXD. 0011: EPWM0 Channel 3 modulete with UART0_TXD. 0100: EPWM0 Channel 4 modulete with UART0_TXD. 0101: EPWM0 Channel 5 modulete with UART0_TXD. 0110: Reserved. 0111: Reserved. 1000: Reserved. 1001: Reserved. 1010: Reserved. 1011: Reserved. 1100: Reserved. 1101: Reserved. 1110: Reserved. 1111: Reserved. Note: This bis is valid while MODEN (SYS_MODCTL[0]) is set to 1.
bits : 4 - 7 (4 bit)
access : read-write


SYS_IPRST1 (IPRST1)

Peripheral Reset Control Register 1
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IPRST1 SYS_IPRST1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIORST TMR0RST TMR1RST TMR2RST TMR3RST ACMP01RST I2C0RST I2C1RST SPI0RST SPI1RST UART0RST UART1RST UART2RST UART3RST UART4RST UART5RST EADCRST

GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO controller normal operation

#1 : 1

GPIO controller reset

End of enumeration elements list.

TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer0 controller normal operation

#1 : 1

Timer0 controller reset

End of enumeration elements list.

TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer1 controller normal operation

#1 : 1

Timer1 controller reset

End of enumeration elements list.

TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer2 controller normal operation

#1 : 1

Timer2 controller reset

End of enumeration elements list.

TMR3RST : Timer3 Controller Reset
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer3 controller normal operation

#1 : 1

Timer3 controller reset

End of enumeration elements list.

ACMP01RST : Analog Comparator 0/1 Controller Reset
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Analog Comparator 0/1 controller normal operation

#1 : 1

Analog Comparator 0/1 controller reset

End of enumeration elements list.

I2C0RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 controller normal operation

#1 : 1

I2C0 controller reset

End of enumeration elements list.

I2C1RST : I2C1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 controller normal operation

#1 : 1

I2C1 controller reset

End of enumeration elements list.

SPI0RST : SPI0 Controller Reset
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 controller normal operation

#1 : 1

SPI0 controller reset

End of enumeration elements list.

SPI1RST : SPI1 Controller Reset
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI1 controller normal operation

#1 : 1

SPI1 controller reset

End of enumeration elements list.

UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 controller normal operation

#1 : 1

UART0 controller reset

End of enumeration elements list.

UART1RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 controller normal operation

#1 : 1

UART1 controller reset

End of enumeration elements list.

UART2RST : UART2 Controller Reset
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART2 controller normal operation

#1 : 1

UART2 controller reset

End of enumeration elements list.

UART3RST : UART3 Controller Reset
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART3 controller normal operation

#1 : 1

UART3 controller reset

End of enumeration elements list.

UART4RST : UART4 Controller Reset
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART4 controller normal operation

#1 : 1

UART4 controller reset

End of enumeration elements list.

UART5RST : UART5 Controller Reset
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART5 controller normal operation

#1 : 1

UART5 controller reset

End of enumeration elements list.

EADCRST : EADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

EADC controller normal operation

#1 : 1

EADC controller reset

End of enumeration elements list.


SYS_SRAM_INTCTL (SRAM_INTCTL)

System SRAM Interrupt Enable Control Register
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_SRAM_INTCTL SYS_SRAM_INTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERRIEN

PERRIEN : SRAM Parity Check Error Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

SRAM parity check error interrupt Disabled

#1 : 1

SRAM parity check error interrupt Enabled

End of enumeration elements list.


SYS_SRAM_STATUS (SRAM_STATUS)

System SRAM Parity Error Status Register
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_SRAM_STATUS SYS_SRAM_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERRIF

PERRIF : SRAM Parity Check Error Flag This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No System SRAM parity error

#1 : 1

System SRAM parity error occur

End of enumeration elements list.


SYS_SRAM_ERRADDR (SRAM_ERRADDR)

System SRAM Parity Check Error Address Register
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYS_SRAM_ERRADDR SYS_SRAM_ERRADDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADDR

ERRADDR : System SRAM Parity Error Address This register shows system SRAM parity error byte address.
bits : 0 - 31 (32 bit)
access : read-only


SYS_SRAM_BISTCTL (SRAM_BISTCTL)

System SRAM BIST Test Control Register
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_SRAM_BISTCTL SYS_SRAM_BISTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRBIST0 SRBIST1 CRBIST PDMABIST

SRBIST0 : SRAM Bank0 BIST Enable Bit (Write Protect) This bit enables BIST test for SRAM bank0. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

system SRAM bank0 BIST Disabled

#1 : 1

system SRAM bank0 BIST Enabled

End of enumeration elements list.

SRBIST1 : SRAM Bank1 BIST Enable Bit (Write Protect) This bit enables BIST test for SRAM bank1. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

system SRAM bank1 BIST Disabled

#1 : 1

system SRAM bank1 BIST Enabled

End of enumeration elements list.

CRBIST : CACHE BIST Enable Bit (Write Protect) This bit enables BIST test for CACHE RAM Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

system CACHE BIST Disabled

#1 : 1

system CACHE BIST Enabled

End of enumeration elements list.

PDMABIST : PDMA BIST Enable Bit (Write Protect) This bit enables BIST test for PDMA RAM Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

system PDMA BIST Disabled

#1 : 1

system PDMA BIST Enabled

End of enumeration elements list.


SYS_SRAM_BISTSTS (SRAM_BISTSTS)

System SRAM BIST Test Status Register
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYS_SRAM_BISTSTS SYS_SRAM_BISTSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRBISTEF0 SRBISTEF1 CRBISTEF PDMABEF SRBEND0 SRBEND1 CRBEND PDMABEND

SRBISTEF0 : 1st System SRAM BIST Fail Flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

1st system SRAM BIST test pass

#1 : 1

1st system SRAM BIST test fail

End of enumeration elements list.

SRBISTEF1 : 2nd System SRAM BIST Fail Flag
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

2nd system SRAM BIST test pass

#1 : 1

2nd system SRAM BIST test fail

End of enumeration elements list.

CRBISTEF : CACHE SRAM BIST Fail Flag
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

System CACHE RAM BIST test pass

#1 : 1

System CACHE RAM BIST test fail

End of enumeration elements list.

PDMABEF : PDMA SRAM BIST Fail Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

PDMA SRAM BIST test pass

#1 : 1

PDMA SRAM BIST test fail

End of enumeration elements list.

SRBEND0 : 1st SRAM BIST Test Finish
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

1st system SRAM BIST active

#1 : 1

1st system SRAM BIST finish

End of enumeration elements list.

SRBEND1 : 2nd SRAM BIST Test Finish
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

#0 : 0

2nd system SRAM BIST is active

#1 : 1

2nd system SRAM BIST finish

End of enumeration elements list.

CRBEND : CACHE SRAM BIST Test Finish
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

#0 : 0

System CACHE RAM BIST is active

#1 : 1

System CACHE RAM BIST test finish

End of enumeration elements list.

PDMABEND : PDMA SRAM BIST Test Finish
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

#0 : 0

PDMA SRAM BIST is active

#1 : 1

PDMA SRAM BIST test finish

End of enumeration elements list.


SYS_IRCTCTL (IRCTCTL)

HIRC Trim Control Register
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IRCTCTL SYS_IRCTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQSEL LOOPSEL RETRYCNT CESTOPEN BOUNDEN REFCKSEL BOUNDARY

FREQSEL : Trim Frequency Selection This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim. During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. Note: Only when the LXT and HIRC is stable, then the FREQSEL setting will be load to HIRC auto trim circuit.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Disable HIRC auto trim function

#01 : 1

Enable HIRC auto trim function and trim HIRC to 48 MHz

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop Selection This field defines that trim value calculation is based on how many reference clocks. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Trim value calculation is based on average difference in 4 clocks of reference clock

#01 : 1

Trim value calculation is based on average difference in 8 clocks of reference clock

#10 : 2

Trim value calculation is based on average difference in 16 clocks of reference clock

#11 : 3

Trim value calculation is based on average difference in 32 clocks of reference clock

End of enumeration elements list.

RETRYCNT : Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. Once the HIRC is locked, the internal trim value update counter will be reset. If the trim value update counter reaches this limitation value and the frequency of HIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Trim retry count limitation is 64 loops

#01 : 1

Trim retry count limitation is 128 loops

#10 : 2

Trim retry count limitation is 256 loops

#11 : 3

Trim retry count limitation is 512 loops

End of enumeration elements list.

CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The trim operation keeps going if clock is inaccurate

#1 : 1

The trim operation is stopped if clock is inaccurate

End of enumeration elements list.

BOUNDEN : Boundary Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Boundary function Disabled

#1 : 1

Boundary function Enabled

End of enumeration elements list.

REFCKSEL : Reference Clock Selection Note: The HIRC trim reference clock is 20 kHz in test mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

HIRC trim reference clock is from LXT (32.768 kHz)

#1 : 1

Reserved.

End of enumeration elements list.

BOUNDARY : Boundary Selection Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. This field shows the update value range. If the difference between the current trim value and the new update trim value is smaller than BOUNDARY value, then the trim value will be update to RC or it will keep the current trim value. Note 1: When the RC clock shift over 0.25% due to temperature condition in lock state, rc_trim circuit will increase or decrease at least 2 to trim value. Note 2: Only when the difference of the current frequency count and the target frequency count is smaller than 0.25% in unlock state, rc_trim circuit will increase or decrease 1 to trim value. Note: This field is effective only when the BOUNDEN(SYS_IRCTCTL[9]) is enabled.
bits : 16 - 20 (5 bit)
access : read-write


SYS_IRCTIEN (IRCTIEN)

HIRC Trim Interrupt Enable Register
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IRCTIEN SYS_IRCTIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFAILIEN CLKEIEN

TFAILIEN : Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU

#1 : 1

Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU

End of enumeration elements list.

CLKEIEN : Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccurate during auto trim operation. If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccurate.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU

#1 : 1

Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU

End of enumeration elements list.


SYS_IRCTISTS (IRCTISTS)

HIRC Trim Interrupt Status Register
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IRCTISTS SYS_IRCTISTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQLOCK TFAILIF CLKERRIF OVBDIF

FREQLOCK : HIRC Frequency Lock Status This bit indicates the HIRC frequency is locked. This is a status bit and does not trigger any interrupt Write 1 to clear this to 0. This bit will be set automatically, if the frequency is locked and the RC_TRIM is enabled.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The internal high-speed oscillator frequency is not locked at 48 MHz yet

#1 : 1

The internal high-speed oscillator frequency is locked at 48 MHz

End of enumeration elements list.

TFAILIF : Trim Failure Interrupt Status This bit indicates that HIRC trim value update limitation count is reached and the HIRC clock frequency is still not locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Trim value update limitation count is not reached

#1 : 1

Trim value update limitation count is reached and HIRC frequency is still not locked

End of enumeration elements list.

CLKERRIF : Clock Error Interrupt Status When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccurate. Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccurate. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock frequency is accurate

#1 : 1

Clock frequency is inaccurate

End of enumeration elements list.

OVBDIF : Over Boundary Status When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. Note 1: Write 1 to clear this flag.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Over boundary coundition did not occur

#1 : 1

Over boundary coundition occurred

End of enumeration elements list.



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