\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x70 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x90 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTEN : HXT Enable Bit (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: When HXT is enabled, GPF.2 and GPF.3 must be set as input mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal (HXT) Disabled
#1 : 1
4~24 MHz external high speed crystal (HXT) Enabled
End of enumeration elements list.
LXTEN : LXT Enable Bit (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: When LXT is enabled, GPF.4 and GPF.5 must be set as input mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz external low speed crystal (LXT) Disabled
#1 : 1
32.768 kHz external low speed crystal (LXT) Enabled
End of enumeration elements list.
HIRCEN : HIRC Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
48 MHz internal high speed RC oscillator (HIRC) Disabled
#1 : 1
48 MHz internal high speed RC oscillator (HIRC) Enabled
End of enumeration elements list.
LIRCEN : LIRC Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
38.4 kHz internal low speed RC oscillator (LIRC) Disabled
#1 : 1
38.4 kHz internal low speed RC oscillator (LIRC) Enabled
End of enumeration elements list.
PDWKDLY : Enable the Wake-up Delay Counter (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 48 MHz internal high speed RC oscillator (HIRC).
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock cycles delay Disabled
#1 : 1
Clock cycles delay Enabled
End of enumeration elements list.
PDWKIEN : Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down mode wake-up interrupt Disabled
#1 : 1
Power-down mode wake-up interrupt Enabled
End of enumeration elements list.
PDWKIF : Power-down Mode Wake-up Interrupt Status
Set by 'Power-down wake-up event', it indicates that resume from Power-down mode'
The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.
Note 1: Write 1 to clear the bit to 0.
Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) is set to 1.
bits : 6 - 6 (1 bit)
access : read-write
PDEN : System Power-down Enable (Write Protect)
When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.
In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.
In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip will not enter Power-down mode after CPU sleep command WFI
#1 : 1
Chip enters Power-down mode after CPU sleep command WFI
End of enumeration elements list.
HIRCSTBS : HIRC Stable Count Select (Write Protect)
Others: Reserved
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
HIRC stable count = 512 clocks
#01 : 1
HIRC stable count = 1024 clocks
#10 : 2
HIRC stable count = 2048 clocks
#11 : 3
HIRC stable count = 256 clocks
End of enumeration elements list.
HXTGAIN : HXT Gain Control Bit (Write Protect)
This is a protected register. Please refer to open lock sequence to program it.
Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off.
Others: Reserved
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
HXT frequency is from 4 MHz to 8 MHz.
HXT frequency is from 4 MHz to 8 MHz. (Crystal)
#001 : 1
HXT frequency is from 8 MHz to 12 MHz.
HXT frequency is from 8 MHz to 12 MHz. (Crystal)
#010 : 2
HXT frequency is from 12 MHz to 16 MHz.
HXT frequency is from 12 MHz to 16 MHz. (Crystal)
#011 : 3
HXT frequency is from 16 MHz to 24 MHz.
HXT frequency is from 16 MHz to 24 MHz. (Crystal)
#100 : 4
HXT frequency is from 4 MHz to 8 MHz. (Resonator)
#101 : 5
HXT frequency is from 8 MHz to 12 MHz. (Resonator)
#110 : 6
HXT frequency is from 12 MHz to 16 MHz. (Resonator)
#111 : 7
HXT frequency is from 16 MHz to 24 MHz. (Resonator)
End of enumeration elements list.
HXTMD : HXT Bypass Mode (Write Protect)
This is a protected register. Please refer to open lock sequence to program it.
Note 2: This bit is write protected. Refer to the SYS_REGCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT work as crystal mode. PF.2 and PF.3 are configured as external high speed crystal (HXT) pins
#1 : 1
HXT works as external clock mode. PF.3 is configured as external clock input pin
End of enumeration elements list.
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKSEL : HCLK Clock Source Selection (Write Protect)
Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
The default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT
#001 : 1
Clock source from LXT
#010 : 2
Clock source from PLL
#011 : 3
Clock source from LIRC
#111 : 7
Clock source from HIRC
End of enumeration elements list.
STCLKSEL : Cortex-M4 SysTick Clock Source Selection (Write Protect)
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT
#001 : 1
Clock source from LXT
#010 : 2
Clock source from HXT/2
#011 : 3
Clock source from HCLK/2
#111 : 7
Clock source from HIRC/2
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTSEL : Watchdog Timer Clock Source Selection (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
Clock source from external low speed crystal oscillator (LXT)
#10 : 2
Clock source from HCLK/2048
#11 : 3
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
TMR0SEL : TIMER0 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from external clock TM0 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR1SEL : TIMER1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from external clock TM1 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR2SEL : TIMER2 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from external clock TM2 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR3SEL : TIMER3 Clock Source Selection
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from external clock TM3 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART0SEL : UART0 Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from external low speed crystal oscillator (LXT)
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART1SEL : UART1 Clock Source Selection
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from external low speed crystal oscillator (LXT)
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
CLKOSEL : Clock Divider Clock Source Selection
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from external low speed crystal oscillator (LXT)
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
WWDTSEL : Window Watchdog Timer Clock Source Selection
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#10 : 2
Clock source from HCLK/2048
#11 : 3
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
Clock Source Select Control Register 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM0SEL : EPWM0 Clock Source Selection
The peripheral clock source of EPWM0 is defined by EPWM0SEL.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from HCLK
#1 : 1
Clock source from PCLK0
End of enumeration elements list.
EPWM1SEL : EPWM1 Clock Source Selection
The peripheral clock source of EPWM1 is defined by EPWM1SEL.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from HCLK
#1 : 1
Clock source from PCLK1
End of enumeration elements list.
SPI0SEL : SPI0 Clock Source Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK1
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
SPI1SEL : SPI1 Clock Source Selection
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK0
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
BPWM0SEL : BPWM0 Clock Source Selection
The peripheral clock source of BPWM0 is defined by BPWM0SEL.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from HCLK
#1 : 1
Clock source from PCLK0
End of enumeration elements list.
BPWM1SEL : BPWM1 Clock Source Selection
The peripheral clock source of BPWM1 is defined by BPWM1SEL.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from HCLK
#1 : 1
Clock source from PCLK1
End of enumeration elements list.
CIR0SEL : CIR0 Clock Source Selection
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from Timer0 clock output (TM0)
#011 : 3
Clock source from internal low speed RC oscillator (LIRC)
#100 : 4
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
Clock Source Select Control Register 3
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART2SEL : UART2 Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from external low speed crystal oscillator (LXT)
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART3SEL : UART3 Clock Source Selection
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from external low speed crystal oscillator (LXT)
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART4SEL : UART4 Clock Source Selection
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from external low speed crystal oscillator (LXT)
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART5SEL : UART5 Clock Source Selection
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from external low speed crystal oscillator (LXT)
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
Clock Divider Number Register 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write
UART0DIV : UART0 Clock Divide Number From UART0 Clock Source
bits : 8 - 11 (4 bit)
access : read-write
UART1DIV : UART1 Clock Divide Number From UART1 Clock Source
bits : 12 - 15 (4 bit)
access : read-write
EADCDIV : EADC Clock Divide Number From EADC Clock Source
bits : 16 - 23 (8 bit)
access : read-write
Clock Divider Number Register 4
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART2DIV : UART2 Clock Divide Number From UART2 Clock Source
bits : 0 - 3 (4 bit)
access : read-write
UART3DIV : UART3 Clock Divide Number From UART3 Clock Source
bits : 4 - 7 (4 bit)
access : read-write
UART4DIV : UART4 Clock Divide Number From UART4 Clock Source
bits : 8 - 11 (4 bit)
access : read-write
UART5DIV : UART5 Clock Divide Number From UART5 Clock Source
bits : 12 - 15 (4 bit)
access : read-write
TRACEDIV : Cortex M4 ETM Trace Clock Divide Number From ETM Trace Clock Source
bits : 24 - 31 (8 bit)
access : read-write
APB Clock Divider Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB0DIV : APB0 Clock Divider
APB0 clock can be divided from HCLK
Others: Reserved.
bits : 0 - 2 (3 bit)
access : read-write
APB1DIV : APB1 Clock Divider
APB1 clock can be divided from HCLK
Others: Reserved.
bits : 4 - 6 (3 bit)
access : read-write
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMACKEN : PDMA Controller Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA peripheral clock Disabled
#1 : 1
PDMA peripheral clock Enabled
End of enumeration elements list.
ISPCKEN : Flash ISP Controller Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash ISP peripheral clock Disabled
#1 : 1
Flash ISP peripheral clock Enabled
End of enumeration elements list.
STCLKEN : Cortex-M4 SysTick Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Cortex-M4 sys tick clock Disabled
#1 : 1
Cortex-M4 sys tick clock Enabled
End of enumeration elements list.
CRCCKEN : CRC Generator Controller Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRC peripheral clock Disabled
#1 : 1
CRC peripheral clock Enabled
End of enumeration elements list.
FMCIDLE : Flash Memory Controller Clock Enable Bit in IDLE Mode
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
FMC clock Disabled when chip is under IDLE mode
#1 : 1
FMC clock Enabled when chip is under IDLE mode
End of enumeration elements list.
TRACECKEN : TRACE Clock Enable Bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
TRACE clock Disabled
#1 : 1
TRACE clock Enabled
End of enumeration elements list.
GPICKEN : GPIOI Clock Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIOI port clock Disabled
#1 : 1
GPIOI port clock Enabled
End of enumeration elements list.
GPACKEN : GPIOA Clock Enable Bit
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIOA port clock Disabled
#1 : 1
GPIOA port clock Enabled
End of enumeration elements list.
GPBCKEN : GPIOB Clock Enable Bit
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIOB port clock Disabled
#1 : 1
GPIOB port clock Enabled
End of enumeration elements list.
GPCCKEN : GPIOC Clock Enable Bit
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIOC port clock Disabled
#1 : 1
GPIOC port clock Enabled
End of enumeration elements list.
GPDCKEN : GPIOD Clock Enable Bit
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIOD port clock Disabled
#1 : 1
GPIOD port clock Enabled
End of enumeration elements list.
GPECKEN : GPIOE Clock Enable Bit
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIOE port clock Disabled
#1 : 1
GPIOE port clock Enabled
End of enumeration elements list.
GPFCKEN : GPIOF Clock Enable Bit
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIOF port clock Disabled
#1 : 1
GPIOF port clock Enabled
End of enumeration elements list.
GPGCKEN : GPIOG Clock Enable Bit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIOG port clock Disabled
#1 : 1
GPIOG port clock Enabled
End of enumeration elements list.
GPHCKEN : GPIOH Clock Enable Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIOH port clock Disabled
#1 : 1
GPIOH port clock Enabled
End of enumeration elements list.
PLL Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBDIV : PLL Feedback Divider Control (Write Protect)
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 8 (9 bit)
access : read-write
INDIV : PLL Input Divider Control (Write Protect)
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 13 (5 bit)
access : read-write
OUTDIV : PLL Output Divider Control (Write Protect)
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 15 (2 bit)
access : read-write
PD : Power-down Mode (Write Protect)
If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode
#1 : 1
PLL is in Power-down mode (default)
End of enumeration elements list.
BP : PLL Bypass Control (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode (default)
#1 : 1
PLL clock output is same as PLL input clock FIN
End of enumeration elements list.
OE : PLL OE (FOUT Enable) Pin Control (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL FOUT Enabled
#1 : 1
PLL FOUT is fixed low
End of enumeration elements list.
PLLSRC : PLL Source Clock Selection (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT)
#1 : 1
PLL source clock from 48 MHz internal high-speed oscillator divided by 4 (HIRC/4)
End of enumeration elements list.
STBSEL : PLL Stable Counter Selection (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz)
#1 : 1
PLL stable time is 16128 PLL source clock (suitable for source clock is larger than 12 MHz)
End of enumeration elements list.
Clock Status Monitor Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HXTSTB : HXT Clock Source Stable Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled
End of enumeration elements list.
LXTSTB : LXT Clock Source Stable Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled
#1 : 1
32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled
End of enumeration elements list.
PLLSTB : Internal PLL Clock Source Stable Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal PLL clock is not stable or disabled
#1 : 1
Internal PLL clock is stable and enabled
End of enumeration elements list.
LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
38.4 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled
#1 : 1
38.4 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled
End of enumeration elements list.
HIRCSTB : HIRC Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
48 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled
#1 : 1
48 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled
End of enumeration elements list.
CLKSFAIL : Clock Switching Fail Flag (Read Only)
This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.
Note: Write 1 to clear the bit to 0.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock switching success
#1 : 1
Clock switching failure
End of enumeration elements list.
Clock Output Control Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Clock Output Frequency Selection
The formula of output frequency is:
Fin is the input clock frequency.
Fout is the frequency of divider output clock.
N is the 4-bit value of FREQSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
CLKOEN : Clock Output Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output function Disabled
#1 : 1
Clock Output function Enabled
End of enumeration elements list.
DIV1EN : Clock Output Divide One Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output will output clock with source frequency divided by FREQSEL
#1 : 1
Clock Output will output clock with source frequency
End of enumeration elements list.
CLK1HZEN : Clock Output 1Hz Enable Bit
Note: Output for 32.768 kHz(LXT) or 38 kHz(LIRC) based on RTCCKSEL(RTC_LXTCTL[7]).
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
1 Hz clock output for 32.768 kHz or 38 kHz frequency compensation Disabled
#1 : 1
1 Hz clock output for 32.768 kHz or 38 kHz frequency compensation Enabled
End of enumeration elements list.
Clock Fail Detector Control Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFDEN : HXT Clock Fail Detector Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled
End of enumeration elements list.
HXTFIEN : HXT Clock Fail Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled
End of enumeration elements list.
LXTFDEN : LXT Clock Fail Detector Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled
#1 : 1
32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled
End of enumeration elements list.
LXTFIEN : LXT Clock Fail Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled
#1 : 1
32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled
End of enumeration elements list.
HXTFQDEN : HXT Clock Frequency Range Detector Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled
End of enumeration elements list.
HXTFQIEN : HXT Clock Frequency Range Detector Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled
End of enumeration elements list.
Clock Fail Detector Status Register
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFIF : HXT Clock Fail Interrupt Flag
Note: Write 1 to clear the bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock is normal
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock stops
End of enumeration elements list.
LXTFIF : LXT Clock Fail Interrupt Flag
Note: Write 1 to clear the bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz external low speed crystal oscillator (LXT) clock is normal
#1 : 1
32.768 kHz external low speed crystal oscillator (LXT) stops
End of enumeration elements list.
HXTFQIF : HXT Clock Frequency Range Detector Interrupt Flag
Note: Write 1 to clear the bit to 0.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal
End of enumeration elements list.
Clock Frequency Range Detector Upper Boundary Register
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPERBD : HXT Clock Frequency Range Detector Upper Boundary Value
The bits define the maximum value of frequency range detector window.
When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will be set to 1.
bits : 0 - 10 (11 bit)
access : read-write
Clock Frequency Range Detector Lower Boundary Register
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOWERBD : HXT Clock Frequency Range Detector Lower Boundary Value
The bits define the minimum value of frequency range detector window.
When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will be set to 1.
bits : 0 - 10 (11 bit)
access : read-write
APB Devices Clock Enable Control Register 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTCKEN : Watchdog Timer Clock Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer clock Disabled
#1 : 1
Watchdog timer clock Enabled
End of enumeration elements list.
RTCCKEN : Real-time-clock APB Interface Clock Enable Bit
This bit is used to control the RTC APB clock only.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC clock Disabled
#1 : 1
RTC clock Enabled
End of enumeration elements list.
TMR0CKEN : Timer0 Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 clock Disabled
#1 : 1
Timer0 clock Enabled
End of enumeration elements list.
TMR1CKEN : Timer1 Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 clock Disabled
#1 : 1
Timer1 clock Enabled
End of enumeration elements list.
TMR2CKEN : Timer2 Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 clock Disabled
#1 : 1
Timer2 clock Enabled
End of enumeration elements list.
TMR3CKEN : Timer3 Clock Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 clock Disabled
#1 : 1
Timer3 clock Enabled
End of enumeration elements list.
CLKOCKEN : CLKO Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
CLKO clock Disabled
#1 : 1
CLKO clock Enabled
End of enumeration elements list.
ACMP01CKEN : Analog Comparator 0/1 Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog comparator 0/1 clock Disabled
#1 : 1
Analog comparator 0/1 clock Enabled
End of enumeration elements list.
I2C0CKEN : I2C0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 clock Disabled
#1 : 1
I2C0 clock Enabled
End of enumeration elements list.
I2C1CKEN : I2C1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 clock Disabled
#1 : 1
I2C1 clock Enabled
End of enumeration elements list.
SPI0CKEN : SPI0 Clock Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 clock Disabled
#1 : 1
SPI0 clock Enabled
End of enumeration elements list.
SPI1CKEN : SPI1 Clock Enable Bit
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI1 clock Disabled
#1 : 1
SPI1 clock Enabled
End of enumeration elements list.
UART0CKEN : UART0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 clock Disabled
#1 : 1
UART0 clock Enabled
End of enumeration elements list.
UART1CKEN : UART1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 clock Disabled
#1 : 1
UART1 clock Enabled
End of enumeration elements list.
UART2CKEN : UART2 Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART2 clock Disabled
#1 : 1
UART2 clock Enabled
End of enumeration elements list.
UART3CKEN : UART3 Clock Enable Bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART3 clock Disabled
#1 : 1
UART3 clock Enabled
End of enumeration elements list.
UART4CKEN : UART4 Clock Enable Bit
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART4 clock Disabled
#1 : 1
UART4 clock Enabled
End of enumeration elements list.
UART5CKEN : UART5 Clock Enable Bit
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART5 clock Disabled
#1 : 1
UART5 clock Enabled
End of enumeration elements list.
EADCCKEN : Enhanced Analog-digital-converter (EADC) Clock Enable Bit
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC clock Disabled
#1 : 1
EADC clock Enabled
End of enumeration elements list.
Power Manager Control Register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMSEL : Power-down Mode Selection (Write Protect)
This is a protected bit. Please refer to open lock sequence to program it.
These bits control chip Power-down mode grade selection when CPU executes WFI/WFE instruction.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Power-down mode is selected. (NPD)
#001 : 1
Reserved.
#010 : 2
Reserved.
#011 : 3
Reserved.
#100 : 4
Reserved.
#101 : 5
Reserved.
#110 : 6
Reserved.
#111 : 7
Reserved.
End of enumeration elements list.
APB Devices Clock Enable Control Register 1
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACCKEN : DAC Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC clock Disabled
#1 : 1
DAC clock Enabled
End of enumeration elements list.
CIR0CKEN : CIR0 Clock Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
CIR0 clock Disabled
#1 : 1
CIR0 clock Enabled
End of enumeration elements list.
EPWM0CKEN : EPWM0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM0 clock Disabled
#1 : 1
EPWM0 clock Enabled
End of enumeration elements list.
EPWM1CKEN : EPWM1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM1 clock Disabled
#1 : 1
EPWM1 clock Enabled
End of enumeration elements list.
BPWM0CKEN : BPWM0 Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0 clock Disabled
#1 : 1
BPWM0 clock Enabled
End of enumeration elements list.
BPWM1CKEN : BPWM1 Clock Enable Bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM1 clock Disabled
#1 : 1
BPWM1 clock Enabled
End of enumeration elements list.
PRNGCKEN : PRNG Clock Enable Bit
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
PRNG clock Disabled
#1 : 1
PRNG clock Enabled
End of enumeration elements list.
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