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DFMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x4C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

DFMC_ISPCTL (ISPCTL)

DFMC_ISPTRG (ISPTRG)

DFMC_ISPADDR (ISPADDR)

DFMC_ISPSTS (ISPSTS)

DFMC_CYCCTL (CYCCTL)

DFMC_ISPDAT (ISPDAT)

DFMC_ISPCMD (ISPCMD)


DFMC_ISPCTL (ISPCTL)

ISP Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFMC_ISPCTL DFMC_ISPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPEN DATAEN ISPFF ISPIFEN

ISPEN : ISP Enable Bit (Write Protect) ISP function enable bit. Set this bit to enable ISP function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

ISP function Disabled

#1 : 1

ISP function Enabled

End of enumeration elements list.

DATAEN : Data Flash Update Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data Flash cannot be updated

#1 : 1

Data Flash can be updated

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: This bit needs to be cleared by writing 1 to it. Data Flash writes to itself if DATAEN is set to 0. Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands Violate the load code read protection Checksum or Flash All One Verification is not executed in their valid range Mass erase is not executed in Data Flash Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

ISPIFEN : ISP Interrupt Enable bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

ISP Interrupt Disabled

#1 : 1

ISP Interrupt Enabled

End of enumeration elements list.


DFMC_ISPTRG (ISPTRG)

ISP Trigger Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFMC_ISPTRG DFMC_ISPTRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPGO

ISPGO : ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

ISP operation is finished

#1 : 1

ISP is progressed

End of enumeration elements list.


DFMC_ISPADDR (ISPADDR)

ISP Address Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFMC_ISPADDR DFMC_ISPADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPADDR

ISPADDR : ISP Address The M471V/M471K is equipped with embedded Data Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. For CRC32 Checksum Calculation command, this field is the Data Flash starting address for checksum calculation, 256 bytes alignment is necessary for CRC32 checksum calculation. For Data Flash32-bit Program, ISP address needs word alignment (4-byte).
bits : 0 - 31 (32 bit)
access : read-write


DFMC_ISPSTS (ISPSTS)

ISP Status Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFMC_ISPSTS DFMC_ISPSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPBUSY ISPFF ALLONE ISPIF

ISPBUSY : ISP Busy Flag (Read Only) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. This bit is the mirror of ISPGO(DFMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

ISP operation is finished

#1 : 1

ISP is progressed

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect) This bit is the mirror of ISPFF (DFMC_ISPCTL[6]), it needs to be cleared by writing 1 to DFMC_ISPCTL[6] or DFMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: Data Flash writes to itself if DATAEN is set to 0. Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands Violate the load code read protection Checksum or Flash All One Verification is not executed in their valid range Mass erase is not executed in Data Flash Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

ALLONE : Data Flash All-one Verification Flag This bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after 'Run Data Flash All-One Verification' complete this bit also can be clear by writing 1
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data Flash bits are not all 1 after 'Run Data Flash All-One Verification' is complete

#1 : 1

All of Data Flash bits are 1 after 'Run Data Flash All-One Verification' is complete

End of enumeration elements list.

ISPIF : ISP Interrupt Flag Note: Write 1 to clear this bit.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

ISP command not finish or ISP fail flag is 0

#1 : 1

ISP command finish or ISP fail is 1

End of enumeration elements list.


DFMC_CYCCTL (CYCCTL)

Data Flash Access Cycle Control Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFMC_CYCCTL DFMC_CYCCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CYCLE

CYCLE : Data Flash Access Cycle Control (Write Protect) This register is updated by software. The optimized HCLK working frequency range is 192 MHz Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

CPU access with zero wait cycle Flash access cycle is 1

#0001 : 1

CPU access with one wait cycle if cache miss Flash access cycle is 1

#0010 : 2

CPU access with two wait cycles if cache miss Flash access cycle is 2

#0011 : 3

CPU access with three wait cycles if cache miss Flash access cycle is 3

#0100 : 4

CPU access with four wait cycles if cache miss Flash access cycle is 4

#0101 : 5

CPU access with five wait cycles if cache miss Flash access cycle is 5

#0110 : 6

CPU access with six wait cycles if cache miss Flash access cycle is 6

#0111 : 7

CPU access with seven wait cycles if cache miss Flash access cycle is 7

#1000 : 8

CPU access with eight wait cycles if cache miss Flash access cycle is 8

End of enumeration elements list.


DFMC_ISPDAT (ISPDAT)

ISP Data Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFMC_ISPDAT DFMC_ISPDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPDAT

ISPDAT : ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write


DFMC_ISPCMD (ISPCMD)

ISP Command Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFMC_ISPCMD DFMC_ISPCMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD

CMD : ISP Command ISP command table is shown below: The other commands are invalid.
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0x00 : 0

Data FLASH Read

0x08 : 8

Read Data Flash All-One Result

0x0b : 11

Read Company ID

0x0c : 12

Read Device ID

0x0d : 13

Read Checksum

0x21 : 33

Data FLASH 32-bit Program

0x22 : 34

Data FLASH Page Erase. Erase any page in Data Flash

0x26 : 38

Data FLASH Mass Erase. Erase all pages in Data Flash

0x28 : 40

Run Data Flash All-One Verification

0x2d : 45

Run Checksum Calculation

End of enumeration elements list.



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