Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x70 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x80 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
address_offset : 0xB0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xC0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
address_offset : 0xF0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x100 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x130 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x140 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x170 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x180 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x1B0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x1C0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x1F0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x200 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x230 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x440 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x450 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x490 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x498 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x800 Bytes (0x0)
size : 0x1B4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x9C0 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xA00 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :
PA I/O Mode Control
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE0 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE1 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE2 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE3 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE4 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE5 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE6 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE7 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE8 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE9 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE10 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE11 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE12 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE13 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE14 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE15 : Port A-I I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2:
The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
PA Pin Value
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIN0 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 0 - 0 (1 bit)
access : read-only
PIN1 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 1 - 1 (1 bit)
access : read-only
PIN2 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 2 - 2 (1 bit)
access : read-only
PIN3 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 3 - 3 (1 bit)
access : read-only
PIN4 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 4 - 4 (1 bit)
access : read-only
PIN5 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 5 - 5 (1 bit)
access : read-only
PIN6 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 6 - 6 (1 bit)
access : read-only
PIN7 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 7 - 7 (1 bit)
access : read-only
PIN8 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 8 - 8 (1 bit)
access : read-only
PIN9 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 9 - 9 (1 bit)
access : read-only
PIN10 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 10 - 10 (1 bit)
access : read-only
PIN11 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 11 - 11 (1 bit)
access : read-only
PIN12 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 12 - 12 (1 bit)
access : read-only
PIN13 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 13 - 13 (1 bit)
access : read-only
PIN14 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 14 - 14 (1 bit)
access : read-only
PIN15 : Port A-I Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 15 - 15 (1 bit)
access : read-only
PE I/O Mode Control
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE Digital Input Path Disable Control
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE Data Output Value
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE Data Output Write Mask
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE Pin Value
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE De-Bounce Enable Control Register
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE Interrupt Trigger Type Control
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE Interrupt Enable Control Register
address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE Interrupt Source Flag
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE Input Schmitt Trigger Enable Register
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE High Slew Rate Control Register
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE Pull-up Selection Register
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA De-Bounce Enable Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBEN0 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN1 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN2 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN3 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN4 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN5 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN6 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN7 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN8 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN9 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN10 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN11 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN12 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN13 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN14 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN15 : Port A-I Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
PF I/O Mode Control
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Digital Input Path Disable Control
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Data Output Value
address_offset : 0x148 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Data Output Write Mask
address_offset : 0x14C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Pin Value
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF De-Bounce Enable Control Register
address_offset : 0x154 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Interrupt Trigger Type Control
address_offset : 0x158 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Interrupt Enable Control Register
address_offset : 0x15C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Interrupt Source Flag
address_offset : 0x160 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Input Schmitt Trigger Enable Register
address_offset : 0x164 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF High Slew Rate Control Register
address_offset : 0x168 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Pull-up Selection Register
address_offset : 0x170 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA Interrupt Trigger Type Control
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE0 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE1 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE2 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE3 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE4 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE5 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE6 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE7 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE8 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE9 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE10 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE11 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE12 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE13 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE14 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE15 : Port A-I Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
PG I/O Mode Control
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG Digital Input Path Disable Control
address_offset : 0x184 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG Data Output Value
address_offset : 0x188 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG Data Output Write Mask
address_offset : 0x18C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG Pin Value
address_offset : 0x190 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG De-Bounce Enable Control Register
address_offset : 0x194 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG Interrupt Trigger Type Control
address_offset : 0x198 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG Interrupt Enable Control Register
address_offset : 0x19C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG Interrupt Source Flag
address_offset : 0x1A0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG Input Schmitt Trigger Enable Register
address_offset : 0x1A4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG High Slew Rate Control Register
address_offset : 0x1A8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG Pull-up Selection Register
address_offset : 0x1B0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA Interrupt Enable Control Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLIEN0 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN1 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN2 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN3 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN4 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN5 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN6 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN7 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN8 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN9 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN10 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN11 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN12 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN13 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN14 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN15 : Port A-I Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
RHIEN0 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN1 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN2 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN3 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN4 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN5 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN6 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN7 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN8 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN9 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN10 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN11 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN12 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN13 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN14 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN15 : Port A-I Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
PH I/O Mode Control
address_offset : 0x1C0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH Digital Input Path Disable Control
address_offset : 0x1C4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH Data Output Value
address_offset : 0x1C8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH Data Output Write Mask
address_offset : 0x1CC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH Pin Value
address_offset : 0x1D0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH De-Bounce Enable Control Register
address_offset : 0x1D4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH Interrupt Trigger Type Control
address_offset : 0x1D8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH Interrupt Enable Control Register
address_offset : 0x1DC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH Interrupt Source Flag
address_offset : 0x1E0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH Input Schmitt Trigger Enable Register
address_offset : 0x1E4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH High Slew Rate Control Register
address_offset : 0x1E8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH Pull-up Selection Register
address_offset : 0x1F0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTSRC0 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC1 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC2 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC3 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC4 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC5 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC6 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC7 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC8 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC9 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC10 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC11 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC12 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC13 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC14 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC15 : Port A-I Pin[n] Interrupt Source Flag
Write Operation :
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
PI I/O Mode Control
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PI Digital Input Path Disable Control
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PI Data Output Value
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PI Data Output Write Mask
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PI Pin Value
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PI De-Bounce Enable Control Register
address_offset : 0x214 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PI Interrupt Trigger Type Control
address_offset : 0x218 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PI Interrupt Enable Control Register
address_offset : 0x21C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PI Interrupt Source Flag
address_offset : 0x220 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PI Input Schmitt Trigger Enable Register
address_offset : 0x224 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PI High Slew Rate Control Register
address_offset : 0x228 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PI Pull-up Selection Register
address_offset : 0x230 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA Input Schmitt Trigger Enable Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMTEN0 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN1 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN2 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN3 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN4 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN5 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN6 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN7 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN8 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN9 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN10 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN11 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN12 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN13 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN14 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN15 : Port A-I Pin[n] Input Schmitt Trigger Enable Bit
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
PA High Slew Rate Control Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSREN0 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN1 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN2 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN3 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN4 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN5 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN6 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN7 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN8 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN9 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN10 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN11 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN12 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN13 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN14 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
HSREN15 : Port A-I Pin[n] High Slew Rate Control
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n output with normal slew rate mode
#01 : 1
Px.n output with high slew rate mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
PA Pull-up Selection Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUSEL0 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL1 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL2 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL3 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL4 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL5 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL6 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL7 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL8 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL9 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL10 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL11 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL12 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL13 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL14 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL15 : Port A-I Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1:
Basically, the pull-up control has following behavior limitation
The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PA Digital Input Path Disable Control
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DINOFF0 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF1 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF2 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF3 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF4 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF5 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF6 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF7 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF8 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF9 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF10 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF11 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF12 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF13 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF14 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF15 : Port A-I Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
PB I/O Mode Control
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Digital Input Path Disable Control
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt De-bounce Control Register
address_offset : 0x440 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBCLKSEL : De-bounce Sampling Cycle Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Sample interrupt input once per 1 clocks
#0001 : 1
Sample interrupt input once per 2 clocks
#0010 : 2
Sample interrupt input once per 4 clocks
#0011 : 3
Sample interrupt input once per 8 clocks
#0100 : 4
Sample interrupt input once per 16 clocks
#0101 : 5
Sample interrupt input once per 32 clocks
#0110 : 6
Sample interrupt input once per 64 clocks
#0111 : 7
Sample interrupt input once per 128 clocks
#1000 : 8
Sample interrupt input once per 256 clocks
#1001 : 9
Sample interrupt input once per 2*256 clocks
#1010 : 10
Sample interrupt input once per 4*256 clocks
#1011 : 11
Sample interrupt input once per 8*256 clocks
#1100 : 12
Sample interrupt input once per 16*256 clocks
#1101 : 13
Sample interrupt input once per 32*256 clocks
#1110 : 14
Sample interrupt input once per 64*256 clocks
#1111 : 15
Sample interrupt input once per 128*256 clocks
End of enumeration elements list.
DBCLKSRC : De-bounce Counter Clock Source Selection
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
De-bounce counter clock source is the HCLK
#1 : 1
De-bounce counter clock source is the internal low speed RC oscillator (LIRC)
End of enumeration elements list.
ICLKON : Interrupt Clock on Mode
Note 1: It is recommended to disable this bit to save system power if no special application concern.
Note 2:The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. If corresponding RHIEN or FLIEN not set to 1, the clock of IO detect circuit is stopped and INTSRC flag cannot be clear also
#1 : 1
All I/O pins edge detection circuit is always active after reset
End of enumeration elements list.
INTn Input Noise Filter Register
address_offset : 0x450 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NFEN : Noise Filter Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise Filter function Disabled
#1 : 1
Noise Filter function Enabled
End of enumeration elements list.
NFSEL : Noise Filter Clock Selection
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
Filter clock = HCLK
#001 : 1
Filter clock = HCLK/2
#010 : 2
Filter clock = HCLK/4
#011 : 3
Filter clock = HCLK/8
#100 : 4
Filter clock = HCLK/16
#101 : 5
Filter clock = HCLK/32
#110 : 6
Filter clock = HCLK/64
#111 : 7
Filter clock = HCLK/128
End of enumeration elements list.
NFCNT : Noise Filter Count
The register bits control the filter counter to count from 0 to NFCNT.
bits : 8 - 10 (3 bit)
access : read-write
INTn Input Noise Filter Register
address_offset : 0x454 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTn Input Noise Filter Register
address_offset : 0x458 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTn Input Noise Filter Register
address_offset : 0x45C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTn Input Noise Filter Register
address_offset : 0x460 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTn Input Noise Filter Register
address_offset : 0x464 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTn Input Noise Filter Register
address_offset : 0x468 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTn Input Noise Filter Register
address_offset : 0x46C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Data Output Value
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT Edge Detect Control Register
address_offset : 0x490 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDETCTL0 : INTn Edge Detect Control Bits
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Not detect
#01 : 1
INTn low to high detection Enable
#10 : 2
INTn high to low detection Enable
#11 : 3
INTn both low to high and high to low detection Enable
End of enumeration elements list.
EDETCTL1 : INTn Edge Detect Control Bits
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Not detect
#01 : 1
INTn low to high detection Enable
#10 : 2
INTn high to low detection Enable
#11 : 3
INTn both low to high and high to low detection Enable
End of enumeration elements list.
EDETCTL2 : INTn Edge Detect Control Bits
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Not detect
#01 : 1
INTn low to high detection Enable
#10 : 2
INTn high to low detection Enable
#11 : 3
INTn both low to high and high to low detection Enable
End of enumeration elements list.
EDETCTL3 : INTn Edge Detect Control Bits
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Not detect
#01 : 1
INTn low to high detection Enable
#10 : 2
INTn high to low detection Enable
#11 : 3
INTn both low to high and high to low detection Enable
End of enumeration elements list.
EDETCTL4 : INTn Edge Detect Control Bits
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Not detect
#01 : 1
INTn low to high detection Enable
#10 : 2
INTn high to low detection Enable
#11 : 3
INTn both low to high and high to low detection Enable
End of enumeration elements list.
EDETCTL5 : INTn Edge Detect Control Bits
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Not detect
#01 : 1
INTn low to high detection Enable
#10 : 2
INTn high to low detection Enable
#11 : 3
INTn both low to high and high to low detection Enable
End of enumeration elements list.
EDETCTL6 : INTn Edge Detect Control Bits
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Not detect
#01 : 1
INTn low to high detection Enable
#10 : 2
INTn high to low detection Enable
#11 : 3
INTn both low to high and high to low detection Enable
End of enumeration elements list.
EDETCTL7 : INTn Edge Detect Control Bits
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Not detect
#01 : 1
INTn low to high detection Enable
#10 : 2
INTn high to low detection Enable
#11 : 3
INTn both low to high and high to low detection Enable
End of enumeration elements list.
Reseved : Reseved
bits : 16 - 31 (16 bit)
access : read-write
INT Edge Detect Interrupt Enable Control Register
address_offset : 0x498 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDIEN0 : INTn Edge Detect Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
INTx Edge Detect Interrupt Disable
#1 : 1
INTx Edge Detect Interrupt Enable
End of enumeration elements list.
EDIEN1 : INTn Edge Detect Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
INTx Edge Detect Interrupt Disable
#1 : 1
INTx Edge Detect Interrupt Enable
End of enumeration elements list.
EDIEN2 : INTn Edge Detect Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
INTx Edge Detect Interrupt Disable
#1 : 1
INTx Edge Detect Interrupt Enable
End of enumeration elements list.
EDIEN3 : INTn Edge Detect Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
INTx Edge Detect Interrupt Disable
#1 : 1
INTx Edge Detect Interrupt Enable
End of enumeration elements list.
EDIEN4 : INTn Edge Detect Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
INTx Edge Detect Interrupt Disable
#1 : 1
INTx Edge Detect Interrupt Enable
End of enumeration elements list.
EDIEN5 : INTn Edge Detect Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
INTx Edge Detect Interrupt Disable
#1 : 1
INTx Edge Detect Interrupt Enable
End of enumeration elements list.
EDIEN6 : INTn Edge Detect Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
INTx Edge Detect Interrupt Disable
#1 : 1
INTx Edge Detect Interrupt Enable
End of enumeration elements list.
EDIEN7 : INTn Edge Detect Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
INTx Edge Detect Interrupt Disable
#1 : 1
INTx Edge Detect Interrupt Enable
End of enumeration elements list.
Reseved : Reseved
bits : 8 - 31 (24 bit)
access : read-write
INT Edge Detect Interrupt Flag Register
address_offset : 0x49C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDIF0 : INTn Edge Detect Interrupt Flag
Note: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Edge Detection happened
#1 : 1
Rising Edge or Falling edge has been detected
End of enumeration elements list.
EDIF1 : INTn Edge Detect Interrupt Flag
Note: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Edge Detection happened
#1 : 1
Rising Edge or Falling edge has been detected
End of enumeration elements list.
EDIF2 : INTn Edge Detect Interrupt Flag
Note: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Edge Detection happened
#1 : 1
Rising Edge or Falling edge has been detected
End of enumeration elements list.
EDIF3 : INTn Edge Detect Interrupt Flag
Note: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Edge Detection happened
#1 : 1
Rising Edge or Falling edge has been detected
End of enumeration elements list.
EDIF4 : INTn Edge Detect Interrupt Flag
Note: This bit is cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Edge Detection happened
#1 : 1
Rising Edge or Falling edge has been detected
End of enumeration elements list.
EDIF5 : INTn Edge Detect Interrupt Flag
Note: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Edge Detection happened
#1 : 1
Rising Edge or Falling edge has been detected
End of enumeration elements list.
EDIF6 : INTn Edge Detect Interrupt Flag
Note: This bit is cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Edge Detection happened
#1 : 1
Rising Edge or Falling edge has been detected
End of enumeration elements list.
EDIF7 : INTn Edge Detect Interrupt Flag
Note: This bit is cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Edge Detection happened
#1 : 1
Rising Edge or Falling edge has been detected
End of enumeration elements list.
Reseved : Reseved
bits : 8 - 31 (24 bit)
access : read-write
PB Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Pin Value
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB De-Bounce Enable Control Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Interrupt Trigger Type Control
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Interrupt Enable Control Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Interrupt Source Flag
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Input Schmitt Trigger Enable Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB High Slew Rate Control Register
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Pull-up Selection Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT0 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT1 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT2 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT3 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT4 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT5 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT6 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT7 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT8 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT9 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT10 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT11 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT12 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT13 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT14 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT15 : Port A-I Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
PC I/O Mode Control
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x800 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDIO : GPIO Px.n Pin Data Input/Output
Writing this bit can control one GPIO pin output value.
Read this register to get GPIO pin status.
For example, writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]), reading PA0_PDIO will return the value of PIN (PA_PIN[0]).
Note 1: The writing operation will not be affected by register DATMSK (Px_DATMSK[n]).
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding GPIO pin set to low
#1 : 1
Corresponding GPIO pin set to high
End of enumeration elements list.
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x804 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x808 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x80C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x810 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x814 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x818 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x81C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x820 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x824 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x828 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x82C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x830 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x834 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x838 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output Register
address_offset : 0x83C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Digital Input Path Disable Control
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x840 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x844 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x848 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x84C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x850 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x854 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x858 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x85C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x860 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x864 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x868 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x86C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x870 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x874 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x878 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output Register
address_offset : 0x87C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Data Output Value
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x880 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x884 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x888 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x88C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x890 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x894 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x898 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x89C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8A0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8A4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8A8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8AC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8B0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8B4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8B8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8BC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8C0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8C4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8C8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8CC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8D0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8D4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8D8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8DC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8E0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8E4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8E8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8EC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8F0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8F4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8F8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8FC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Pin Value
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x900 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x904 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x908 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x90C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x910 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x914 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x918 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x91C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x920 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x924 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x928 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x92C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x930 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x934 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x938 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.n Pin Data Input/Output Register
address_offset : 0x93C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC De-Bounce Enable Control Register
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x940 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x944 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x948 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x94C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x950 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x954 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x958 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x95C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x960 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x964 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x968 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x96C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x970 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x974 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x978 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output Register
address_offset : 0x97C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Interrupt Trigger Type Control
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PG.n Pin Data Input/Output Register
address_offset : 0x980 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PG.n Pin Data Input/Output Register
address_offset : 0x984 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PG.n Pin Data Input/Output Register
address_offset : 0x988 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PG.n Pin Data Input/Output Register
address_offset : 0x98C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PG.n Pin Data Input/Output Register
address_offset : 0x990 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PG.n Pin Data Input/Output Register
address_offset : 0x994 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PG.n Pin Data Input/Output Register
address_offset : 0x998 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PG.n Pin Data Input/Output Register
address_offset : 0x99C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PG.n Pin Data Input/Output Register
address_offset : 0x9A0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PG.n Pin Data Input/Output Register
address_offset : 0x9A4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PG.n Pin Data Input/Output Register
address_offset : 0x9A8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PG.n Pin Data Input/Output Register
address_offset : 0x9AC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PG.n Pin Data Input/Output Register
address_offset : 0x9B0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Interrupt Enable Control Register
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PH.n Pin Data Input/Output Register
address_offset : 0x9C0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PH.n Pin Data Input/Output Register
address_offset : 0x9C4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PH.n Pin Data Input/Output Register
address_offset : 0x9C8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PH.n Pin Data Input/Output Register
address_offset : 0x9CC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PH.n Pin Data Input/Output Register
address_offset : 0x9D0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PH.n Pin Data Input/Output Register
address_offset : 0x9D4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PH.n Pin Data Input/Output Register
address_offset : 0x9D8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PH.n Pin Data Input/Output Register
address_offset : 0x9DC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PH.n Pin Data Input/Output Register
address_offset : 0x9E0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PH.n Pin Data Input/Output Register
address_offset : 0x9E4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PH.n Pin Data Input/Output Register
address_offset : 0x9E8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PH.n Pin Data Input/Output Register
address_offset : 0x9EC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PH.n Pin Data Input/Output Register
address_offset : 0x9F0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Interrupt Source Flag
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PI.n Pin Data Input/Output Register
address_offset : 0xA00 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PI.n Pin Data Input/Output Register
address_offset : 0xA04 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PI.n Pin Data Input/Output Register
address_offset : 0xA08 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PI.n Pin Data Input/Output Register
address_offset : 0xA0C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PI.n Pin Data Input/Output Register
address_offset : 0xA10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PI.n Pin Data Input/Output Register
address_offset : 0xA14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PI.n Pin Data Input/Output Register
address_offset : 0xA18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PI.n Pin Data Input/Output Register
address_offset : 0xA1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Input Schmitt Trigger Enable Register
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC High Slew Rate Control Register
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Pull-up Selection Register
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA Data Output Write Mask
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATMSK0 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK1 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK2 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK3 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK4 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK5 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK6 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK7 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK8 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK9 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK10 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK11 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK12 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK13 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK14 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK15 : Port A-I Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PC.15/PG.0/PG.1/PG.5~PG.8/PH.0~PH.3/PH.12~PH.15/PI.6~PI.15 pins are not available.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
PD I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Digital Input Path Disable Control
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Data Output Value
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Pin Value
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD De-Bounce Enable Control Register
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Interrupt Trigger Type Control
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Interrupt Enable Control Register
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Interrupt Source Flag
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Input Schmitt Trigger Enable Register
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD High Slew Rate Control Register
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Pull-up Selection Register
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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