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CIR0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x18 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x38 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

CIR_CTL

CIR_INTCTL

CIR_HDBOUND

CIR_D0BOUND

CIR_D1BOUND

CIR_SPBOUND

CIR_ENDBOUND

CIR_LTVR

CIR_RDBC

CIR_CMPCTL

CIR_DATA0

CIR_DATA1

CIR_STATUS


CIR_CTL

CIR Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR_CTL CIR_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTEN POLINV ERRBYP PATTYP DBSEL FOSTRS PSCALER

CNTEN : CIR Counter Enable Note: When user changes CNTEN (CIR_CTL[0]) from 0 to 1, system will generate a signal to initialize all interrupt flags, RBITCNT (CIR_RDBC[5:0])and ITVR (CIR_ITVR[31:0]).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

CIR counter Disabled

#1 : 1

CIR counter Enabled

End of enumeration elements list.

POLINV : CIR Input Polarity Inverse
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

CIR input polarity is normal

#1 : 1

CIR input polarity is inversed

End of enumeration elements list.

ERRBYP : Error Pattern Bypass Note: 1.If user clears RERRF(CIR_STATUS[6]), then CIR will keep to convert data and store in CIR_DATAx. 2.User must set ERRBYP (CIR_CTL[4]) to 1 before entering Power-down mode.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data will be dropped if RERRF(CIR_STATUS[6]) is 1

#1 : 1

Data will keep to save in DATAx if RERRF(CIR_STATUS[6]) flag is 1

End of enumeration elements list.

PATTYP : CIR Pattern Format Selection
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#00 : 0

Standardized positive edge mode

#01 : 1

Standardized negative edge mode

#10 : 2

Flexible positive edge mode

#11 : 3

Reserved.

End of enumeration elements list.

DBSEL : Debounce Sampling Selection
bits : 9 - 10 (2 bit)
access : read-write

Enumeration:

#00 : 0

CIR noise filter Disabled

#01 : 1

CIR input debounce count Enabled with two sample matched

#10 : 2

CIR input debounce count Enabled with three sample matched

#11 : 3

CIR input debounce count Enabled with four sample matched

End of enumeration elements list.

FOSTRS : Filter Output Signal Stored in Register Selection
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Filter output signal stored in CIR_STATUS[16] Disabled

#1 : 1

Filter output signal stored in CIR_STATUS[16] Enabled

End of enumeration elements list.

PSCALER : Sampling Clock Prescaler Note: The sampling clock should be less than PCLK1.
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

No prescaler

#001 : 1

Prescaler is 2 clocks

#010 : 2

Prescaler is 4 clocks

#011 : 3

Prescaler is 8 clocks

#100 : 4

Prescaler is 16 clocks

#101 : 5

Prescaler is 32 clocks

#110 : 6

Prescaler is 64 clocks

#111 : 7

Prescaler is 128 clocks

End of enumeration elements list.


CIR_INTCTL

CIR Interrupt Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR_INTCTL CIR_INTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPMIEN D1PMIEN D0PMIEN HPMIEN RBUFIEN DRECIEN PERRIEN CMPMIEN EPMIEN RBMIEN PDWKIEN

SPMIEN : Special Pattern Match Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Special pattern match interrupt Disabled

#1 : 1

Special pattern match interrupt Enabled

End of enumeration elements list.

D1PMIEN : Data1 Pattern Match Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data1 pattern match interrupt Disabled

#1 : 1

Data1 pattern match interrupt Enabled

End of enumeration elements list.

D0PMIEN : Data0 Pattern Match Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data0 pattern match interrupt Disabled

#1 : 1

Data0 pattern match interrupt Enabled

End of enumeration elements list.

HPMIEN : Header Pattern Match Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Header pattern match interrupt Disabled

#1 : 1

Header pattern match interrupt Enabled

End of enumeration elements list.

RBUFIEN : Receive Buffer Full Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receive buffer full interrupt Disabled

#1 : 1

Receive buffer full interrupt Enabled

End of enumeration elements list.

DRECIEN : Data Receive Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data receive interrupt Disabled

#1 : 1

Data receive interrupt Enabled

End of enumeration elements list.

PERRIEN : Pattern Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pattern error interrupt Disabled

#1 : 1

Pattern error interrupt Enabled

End of enumeration elements list.

CMPMIEN : Compare Match Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Compare match interrupt Disabled

#1 : 1

Compare match interrupt Enabled

End of enumeration elements list.

EPMIEN : End Pattern Match Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

End pattern match interrupt Disabled

#1 : 1

End pattern match interrupt Enabled

End of enumeration elements list.

RBMIEN : Receive Bit Match Interrupt Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receive bit match interrupt Disabled

#1 : 1

Receive bit match interrupt Enabled

End of enumeration elements list.

PDWKIEN : Power Down Wake-up interrupt Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power down wake-up interrupt Disabled

#1 : 1

Power down wake-up interrupt Enabled

End of enumeration elements list.


CIR_HDBOUND

CIR Header Pattern Boundry Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR_HDBOUND CIR_HDBOUND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBOUND HBOUND

LBOUND : Low Boundary Header Pattern Lower limit of Header pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Header pattern boundary.
bits : 0 - 10 (11 bit)
access : read-write

HBOUND : High Boundary Header Pattern Upper limit of Header pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Header pattern boundary.
bits : 16 - 26 (11 bit)
access : read-write


CIR_D0BOUND

CIR Data 0 Pattern Boundry Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR_D0BOUND CIR_D0BOUND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBOUND HBOUND

LBOUND : Low Boundary Data0 Pattern Lower limit of Data 0 pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Data0 pattern boundary.
bits : 0 - 10 (11 bit)
access : read-write

HBOUND : High Boundary Data0 Pattern Upper limit of Data 0 pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Data0 pattern boundary.
bits : 16 - 26 (11 bit)
access : read-write


CIR_D1BOUND

CIR Data 1 Pattern Boundry Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR_D1BOUND CIR_D1BOUND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBOUND HBOUND

LBOUND : Low Boundary Data 1 Pattern Upper limit of Data 1 pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Data1 pattern boundary.
bits : 0 - 10 (11 bit)
access : read-write

HBOUND : High Boundary Data 1 Pattern Upper limit of Data 1 pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Data1 pattern boundary.
bits : 16 - 26 (11 bit)
access : read-write


CIR_SPBOUND

CIR Special Pattern Boundry Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR_SPBOUND CIR_SPBOUND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBOUND HBOUND

LBOUND : Low Boundary Special Pattern Lower limit of Special pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Special pattern boundary.
bits : 0 - 10 (11 bit)
access : read-write

HBOUND : High Boundary Special Pattern Upper limit of Special pattern input range. Note: If HBOUND and LBOUND are equal to 0, the CIR controller will not monitor the Special pattern boundary.
bits : 16 - 26 (11 bit)
access : read-write


CIR_ENDBOUND

CIR End Pattern Boundry Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR_ENDBOUND CIR_ENDBOUND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBOUND

LBOUND : Low Boundary End Pattern Lower limit of End pattern input range.
bits : 0 - 10 (11 bit)
access : read-write


CIR_LTVR

CIR Latch Timer Value Register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIR_LTVR CIR_LTVR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTV

LTV : Latch Timer Value The register is used to record CIR latch timer value. Note: User can only read this register when HPMF (CIR_STATUS[3]), D0PMF (CIR_STATUS[2]), D1PMF (CIR_STATUS[1]), SPMF (CIR_STATUS[0]) or RERRF (CIR_STATUS[6]) occurred.
bits : 0 - 10 (11 bit)
access : read-only


CIR_RDBC

CIR Receive Data Bit Count Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR_RDBC CIR_RDBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBITCNT BCCMEN RBITCMP

RBITCNT : Receive Data Bit Counts RBITCNT (CIR_RDBC[5:0]) correspond to CIR_DATA0 and CIR_DATA1 when CIR starts to convert data. Note: 1. User can write 1 to CIR_RDBC[5:0] to clean RBITCNT (CIR_RDBC[5:0]) value. 2. RBITCNT (CIR_RDBC[5:0]) value indicates the amount of data DATA0 (CIR_DATA0) that has already been confirmed. 3. The maximum value of RBITCNT (CIR_RDBC[5:0]) is 7'h40.
bits : 0 - 6 (7 bit)
access : read-write

BCCMEN : Bit Count Compared Match Selection
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit count compared match function Disabled

#1 : 1

Bit count compared match function Enabled

End of enumeration elements list.

RBITCMP : Receive Data Bit Compare Data User can limit the converted data length by RBITCMP register. When CIR starts to convert data and RBITCNT(CIR_RDBC[5:0]) is equal to RBITCMP (CIR_RDBC[21:16]), the flag RBMF(CIR_STATUS[9]) will be asserted Note: The maximum value of RBITCMP (CIR_RDBC[22:16]) is 7'h40.
bits : 16 - 22 (7 bit)
access : read-write


CIR_CMPCTL

CIR Data Compare Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR_CMPCTL CIR_CMPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPDAT DCMPEN CMPMSK CMPVALID

CMPDAT : Compared Match Data This bit field should be filled with the expected data. It will be compared with CIR_DATA0[N:0]. Note: N is determined by CMPVALID(CIR_CMPCTL[26:24]).
bits : 0 - 7 (8 bit)
access : read-write

DCMPEN : Data Compared Match Function Selection
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data compared match function Disabled

#1 : 1

Data compared match function Enabled

End of enumeration elements list.

CMPMSK : Data Compared Mask Initialization Note: This bit is auto cleared by hardware.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Re-initialize the data compared match function to monitor DATA0[N:0] (CIR_DATA0[N:0)

End of enumeration elements list.

CMPVALID : Data Compared Valid Bit Selection Note: The sampling clock should be less than PCLK1.
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 0

Compare bit 0

#001 : 1

Compare bit 0 to bit 1

#010 : 2

Compare bit 0 to bit 2

#011 : 3

Compare bit 0 to bit 3

#100 : 4

Compare bit 0 to bit 4

#101 : 5

Compare bit 0 to bit 5

#110 : 6

Compare bit 0 to bit 6

#111 : 7

Compare bit 0 to bit 7

End of enumeration elements list.


CIR_DATA0

CIR Receive Data0 Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR_DATA0 CIR_DATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA0

DATA0 : CIR DATA0 Register CIR converts data and stores the data in Data0 when RBITCNT(CIR_RDBC[5:0]) value is between 0 to 31. Note: User can write 1 to CIR_DATA0[31:0] to clean DATA0 value only when the register CNTEN(CIR_CTL[0]) is set to 0.
bits : 0 - 31 (32 bit)
access : read-write


CIR_DATA1

CIR Receive Data1 Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR_DATA1 CIR_DATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA1

DATA1 : CIR DATA1 Register CIR converts data and stores the data in Data1 when RBITCNT(CIR_RDBC[5:0]) value is between 32 to 63. Note: User can write 1 to CIR_DATA1[31:0] to clean DATA1 value only when the register CNTEN(CIR_CTL[0]) is set to 0.
bits : 0 - 31 (32 bit)
access : read-write


CIR_STATUS

CIR Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR_STATUS CIR_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPMF D1PMF D0PMF HPMF RBUFF DRECF RERRF COMPMF EPMF RBMF PDWKF NFOS RBITCBS

SPMF : Special Pattern Match Flag Note: This bit is only cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Special pattern never happened

#1 : 1

Special pattern happened

End of enumeration elements list.

D1PMF : Data1 Pattern Match Flag Note: This bit is only cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data1 pattern never happened

#1 : 1

Data1 pattern happened

End of enumeration elements list.

D0PMF : Data0 Pattern Match Flag Note: This bit is only cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data0 pattern never happened

#1 : 1

Data0 pattern happened

End of enumeration elements list.

HPMF : Header Pattern Match Flag Note: This bit is only cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Header pattern never happened

#1 : 1

Header pattern happened

End of enumeration elements list.

RBUFF : Receiving Buffer Full Flag Note: This bit is only cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receiving buffer full never happened

#1 : 1

Receiving buffer full happened

End of enumeration elements list.

DRECF : Data Receive Flag Note: This bit is only cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

CIR has not started to convert data

#1 : 1

CIR has started to convert data

End of enumeration elements list.

RERRF : Receive Error Flag Note: This bit is only cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receive error never happened

#1 : 1

Receive error happened

End of enumeration elements list.

COMPMF : Compare Match Flag Note: This bit is only cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Compare match never happened

#1 : 1

Compare match happened

End of enumeration elements list.

EPMF : End Pattern Match Flag Note: This bit is only cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

End pattern match never happened

#1 : 1

End pattern match happened

End of enumeration elements list.

RBMF : Receive Bit Match Flag Note: This bit is only cleared by writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receive bit match never happened

#1 : 1

Receive bit match happened

End of enumeration elements list.

PDWKF : Power Down Wake Up Flag Note: This bit is only cleared by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power down wake up never happened

#1 : 1

Power down wake up happened

End of enumeration elements list.

NFOS : Noise Filter Output Signal Status
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Noise filter output value is 0

#1 : 1

Noise filter output value is 1

End of enumeration elements list.

RBITCBS : RBITCNT Busy Clearing Status
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

RBITCNT has completed the clearing process when user writes 1 to RBITCNT(CIR_RDBC[5:0]) or user changes CNTEN (CIR_CTL[0]) from 0 to 1, and system will generate a signal to initialize RBITCNT (CIR_RDBC[5:0])

#1 : 1

RBITCNT undergoes clearing process when user writes 1 to RBITCNT(CIR_RDBC[5:0]) or user changes CNTEN (CIR_CTL[0]) from 0 to 1, and system will generate a signal to initialize RBITCNT (CIR_RDBC[5:0])

End of enumeration elements list.



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