\n

EADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x80 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection :

address_offset : 0xD0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x114 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x130 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x140 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x200 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xFF8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

EADC_DAT0 (DAT0)

EADC_DAT4 (DAT4)

EADC_DDAT0 (DDAT0)

EADC_DDAT1 (DDAT1)

EADC_DDAT2 (DDAT2)

EADC_DDAT3 (DDAT3)

EADC_CALCTL (CALCTL)

EADC_CALSR (CALSR)

EADC_PDMACTL (PDMACTL)

EADC_DAT5 (DAT5)

EADC_M0CTL1 (M0CTL1)

EADC_M1CTL1 (M1CTL1)

EADC_M2CTL1 (M2CTL1)

EADC_M3CTL1 (M3CTL1)

EADC_M4CTL1 (M4CTL1)

EADC_M5CTL1 (M5CTL1)

EADC_M6CTL1 (M6CTL1)

EADC_M7CTL1 (M7CTL1)

EADC_M8CTL1 (M8CTL1)

EADC_M9CTL1 (M9CTL1)

EADC_M10CTL1 (M10CTL1)

EADC_M11CTL1 (M11CTL1)

EADC_M12CTL1 (M12CTL1)

EADC_M13CTL1 (M13CTL1)

EADC_M14CTL1 (M14CTL1)

EADC_M15CTL1 (M15CTL1)

EADC_DAT6 (DAT6)

EADC_M16CTL1 (M16CTL1)

EADC_M17CTL1 (M17CTL1)

EADC_M18CTL1 (M18CTL1)

EADC_M19CTL1 (M19CTL1)

EADC_M20CTL1 (M20CTL1)

EADC_M21CTL1 (M21CTL1)

EADC_M22CTL1 (M22CTL1)

EADC_M23CTL1 (M23CTL1)

EADC_DAT7 (DAT7)

EADC_DAT8 (DAT8)

EADC_DAT19 (DAT19)

EADC_DAT20 (DAT20)

EADC_DAT21 (DAT21)

EADC_DAT22 (DAT22)

EADC_DAT23 (DAT23)

EADC_DAT24 (DAT24)

EADC_DAT25 (DAT25)

EADC_DAT26 (DAT26)

EADC_SCTL19 (SCTL19)

EADC_SCTL20 (SCTL20)

EADC_SCTL21 (SCTL21)

EADC_SCTL22 (SCTL22)

EADC_SCTL23 (SCTL23)

EADC_SCTL24 (SCTL24)

EADC_SCTL25 (SCTL25)

EADC_SCTL26 (SCTL26)

EADC_DAT9 (DAT9)

EADC_DAT10 (DAT10)

EADC_DAT11 (DAT11)

EADC_DAT12 (DAT12)

EADC_DAT13 (DAT13)

EADC_DAT14 (DAT14)

EADC_DAT15 (DAT15)

EADC_DAT1 (DAT1)

EADC_DAT16 (DAT16)

EADC_DAT17 (DAT17)

EADC_DAT18 (DAT18)

EADC_CURDAT (CURDAT)

EADC_CTL (CTL)

EADC_SWTRG (SWTRG)

EADC_PENDSTS (PENDSTS)

EADC_OVSTS (OVSTS)

EADC_CTL1 (CTL1)

EADC_DAT2 (DAT2)

EADC_SCTL0 (SCTL0)

EADC_SCTL1 (SCTL1)

EADC_SCTL2 (SCTL2)

EADC_SCTL3 (SCTL3)

EADC_SCTL4 (SCTL4)

EADC_SCTL5 (SCTL5)

EADC_SCTL6 (SCTL6)

EADC_SCTL7 (SCTL7)

EADC_SCTL8 (SCTL8)

EADC_SCTL9 (SCTL9)

EADC_SCTL10 (SCTL10)

EADC_SCTL11 (SCTL11)

EADC_SCTL12 (SCTL12)

EADC_SCTL13 (SCTL13)

EADC_SCTL14 (SCTL14)

EADC_SCTL15 (SCTL15)

EADC_DAT3 (DAT3)

EADC_SCTL16 (SCTL16)

EADC_SCTL17 (SCTL17)

EADC_SCTL18 (SCTL18)

EADC_INTSRC0 (INTSRC0)

EADC_INTSRC1 (INTSRC1)

EADC_INTSRC2 (INTSRC2)

EADC_INTSRC3 (INTSRC3)

EADC_CMP0 (CMP0)

EADC_CMP1 (CMP1)

EADC_CMP2 (CMP2)

EADC_CMP3 (CMP3)

EADC_STATUS0 (STATUS0)

EADC_STATUS1 (STATUS1)

EADC_STATUS2 (STATUS2)

EADC_STATUS3 (STATUS3)

EADC_VREF (VREF)


EADC_DAT0 (DAT0)

EADC Data Register 0 for Sample Module 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT0 EADC_DAT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT OV VALID

RESULT : EADC Conversion Result This field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. Note: When operating in oversampling mode, RESULT[15:0] can represent oversampling results.
bits : 0 - 15 (16 bit)
access : read-only

OV : Overrun Flag If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. Note: It is cleared by hardware after EADC_DAT register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

Data in RESULT[11:0] is recent conversion result

#1 : 1

Data in RESULT[11:0] is overwrite

End of enumeration elements list.

VALID : Valid Flag This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

#0 : 0

Data in RESULT[11:0] bits is not valid

#1 : 1

Data in RESULT[11:0] bits is valid

End of enumeration elements list.


EADC_DAT4 (DAT4)

EADC Data Register 4 for Sample Module 4
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT4 EADC_DAT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DDAT0 (DDAT0)

EADC Double Data Register 0 for Sample Module 0
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EADC_DDAT0 EADC_DDAT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT OV VALID

RESULT : EADC Conversion Results This field contains 12 bits conversion results. The 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
bits : 0 - 15 (16 bit)
access : read-only

OV : Overrun Flag If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after EADC_DDAT register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

Double Data in RESULT (EADC_DDATn[15:0], n=0~3) is recent conversion result

#1 : 1

Double Data in RESULT (EADC_DDATn[15:0], n=0~3) is overwrite

End of enumeration elements list.

VALID : Valid Flag
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

#0 : 0

Double data in RESULT (EADC_DDATn[15:0]) is not valid

#1 : 1

Double data in RESULT (EADC_DDATn[15:0]) is valid

End of enumeration elements list.


EADC_DDAT1 (DDAT1)

EADC Double Data Register 1 for Sample Module 1
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DDAT1 EADC_DDAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DDAT2 (DDAT2)

EADC Double Data Register 2 for Sample Module 2
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DDAT2 EADC_DDAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DDAT3 (DDAT3)

EADC Double Data Register 3 for Sample Module 3
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DDAT3 EADC_DDAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_CALCTL (CALCTL)

EADC Calibration Control Register
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_CALCTL EADC_CALCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAL CALIE CALADDR CALWRDATA

CAL : Calibration Enable Bit Note: This bit is hardware auto cleared when calibration is done
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

= Calibration Disabled

#1 : 1

= Calibration Enabled

End of enumeration elements list.

CALIE : Calibration Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Calibration interrupt Disabled

#1 : 1

Calibration interrupt Enabled

End of enumeration elements list.

CALADDR : Calibration Data Address
bits : 8 - 12 (5 bit)
access : read-write

CALWRDATA : Calibration Write Data
bits : 24 - 31 (8 bit)
access : read-write


EADC_CALSR (CALSR)

EADC Calibration Status Register
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_CALSR EADC_CALSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALIF

CALIF : Calibration Finish Interrupt Flag If calibration is finished, this flag will be set to 1. It is cleared by writing 1 to it.
bits : 16 - 16 (1 bit)
access : read-write


EADC_PDMACTL (PDMACTL)

EADC PDMA Control Register
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_PDMACTL EADC_PDMACTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMATEN

PDMATEN : PDMA Transfer Enable Bit When EADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 26) register, user can enable this bit to generate a PDMA data transfer request.
bits : 0 - 26 (27 bit)
access : read-write

Enumeration:

0 : 0

PDMA data transfer Disabled

1 : 1

PDMA data transfer Enabled

End of enumeration elements list.


EADC_DAT5 (DAT5)

EADC Data Register 5 for Sample Module 5
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT5 EADC_DAT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M0CTL1 (M0CTL1)

EADC Sample Module0 Control Register 1
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M0CTL1 EADC_M0CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALIGN AVG ACU

ALIGN : Alignment Selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The conversion result will be right aligned in data register

#1 : 1

The conversion result will be left aligned in data register

End of enumeration elements list.

AVG : Average Mode Selection
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion results will be stored in data register without averaging

#1 : 1

Conversion results in data register will be averaged

End of enumeration elements list.

ACU : Number of Accumulated Conversion Results Selection
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

#0000 : 0

1 conversion result will be accumulated

#0001 : 1

2 conversion result will be accumulated

#0010 : 2

4 conversion result will be accumulated

#0011 : 3

8 conversion result will be accumulated

#0100 : 4

16 conversion result will be accumulated

#0101 : 5

32 conversion result will be accumulated

#0110 : 6

64 conversion result will be accumulated

#0111 : 7

128 conversion result will be accumulated

#1000 : 8

256 conversion result will be accumulated

End of enumeration elements list.


EADC_M1CTL1 (M1CTL1)

EADC Sample Module1 Control Register 1
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M1CTL1 EADC_M1CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M2CTL1 (M2CTL1)

EADC Sample Module2 Control Register 1
address_offset : 0x148 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M2CTL1 EADC_M2CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M3CTL1 (M3CTL1)

EADC Sample Module3 Control Register 1
address_offset : 0x14C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M3CTL1 EADC_M3CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M4CTL1 (M4CTL1)

EADC Sample Module4 Control Register 1
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M4CTL1 EADC_M4CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M5CTL1 (M5CTL1)

EADC Sample Module5 Control Register 1
address_offset : 0x154 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M5CTL1 EADC_M5CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M6CTL1 (M6CTL1)

EADC Sample Module6 Control Register 1
address_offset : 0x158 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M6CTL1 EADC_M6CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M7CTL1 (M7CTL1)

EADC Sample Module7 Control Register 1
address_offset : 0x15C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M7CTL1 EADC_M7CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M8CTL1 (M8CTL1)

EADC Sample Module8 Control Register 1
address_offset : 0x160 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M8CTL1 EADC_M8CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M9CTL1 (M9CTL1)

EADC Sample Module9 Control Register 1
address_offset : 0x164 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M9CTL1 EADC_M9CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M10CTL1 (M10CTL1)

EADC Sample Module10 Control Register 1
address_offset : 0x168 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M10CTL1 EADC_M10CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M11CTL1 (M11CTL1)

EADC Sample Module11 Control Register 1
address_offset : 0x16C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M11CTL1 EADC_M11CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M12CTL1 (M12CTL1)

EADC Sample Module12 Control Register 1
address_offset : 0x170 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M12CTL1 EADC_M12CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M13CTL1 (M13CTL1)

EADC Sample Module13 Control Register 1
address_offset : 0x174 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M13CTL1 EADC_M13CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M14CTL1 (M14CTL1)

EADC Sample Module14 Control Register 1
address_offset : 0x178 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M14CTL1 EADC_M14CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M15CTL1 (M15CTL1)

EADC Sample Module15 Control Register 1
address_offset : 0x17C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M15CTL1 EADC_M15CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT6 (DAT6)

EADC Data Register 6 for Sample Module 6
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT6 EADC_DAT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M16CTL1 (M16CTL1)

EADC Sample Module16 Control Register 1
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M16CTL1 EADC_M16CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M17CTL1 (M17CTL1)

EADC Sample Module17 Control Register 1
address_offset : 0x184 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M17CTL1 EADC_M17CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M18CTL1 (M18CTL1)

EADC Sample Module18 Control Register 1
address_offset : 0x188 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M18CTL1 EADC_M18CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M19CTL1 (M19CTL1)

EADC Sample Module19 Control Register 1
address_offset : 0x18C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M19CTL1 EADC_M19CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M20CTL1 (M20CTL1)

EADC Sample Module20 Control Register 1
address_offset : 0x190 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M20CTL1 EADC_M20CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M21CTL1 (M21CTL1)

EADC Sample Module21 Control Register 1
address_offset : 0x194 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M21CTL1 EADC_M21CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M22CTL1 (M22CTL1)

EADC Sample Module22 Control Register 1
address_offset : 0x198 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M22CTL1 EADC_M22CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_M23CTL1 (M23CTL1)

EADC Sample Module23 Control Register 1
address_offset : 0x19C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_M23CTL1 EADC_M23CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT7 (DAT7)

EADC Data Register 7 for Sample Module 7
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT7 EADC_DAT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT8 (DAT8)

EADC Data Register 8 for Sample Module 8
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT8 EADC_DAT8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT19 (DAT19)

EADC Data Register 19 for Sample Module 19
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT19 EADC_DAT19 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT OV VALID

RESULT : EADC Conversion Result This field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
bits : 0 - 15 (16 bit)
access : read-only

OV : Overrun Flag If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. Note: It is cleared by hardware after EADC_DAT register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

Data in RESULT[11:0] is recent conversion result

#1 : 1

Data in RESULT[11:0] is overwrite

End of enumeration elements list.

VALID : Valid Flag This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

#0 : 0

Data in RESULT[11:0] bits is not valid

#1 : 1

Data in RESULT[11:0] bits is valid

End of enumeration elements list.


EADC_DAT20 (DAT20)

EADC Data Register 20 for Sample Module 20
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT20 EADC_DAT20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT21 (DAT21)

EADC Data Register 21 for Sample Module 21
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT21 EADC_DAT21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT22 (DAT22)

EADC Data Register 22 for Sample Module 22
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT22 EADC_DAT22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT23 (DAT23)

EADC Data Register 23 for Sample Module 23
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT23 EADC_DAT23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT24 (DAT24)

EADC Data Register 24 for Sample Module 24
address_offset : 0x214 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT24 EADC_DAT24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT25 (DAT25)

EADC Data Register 25 for Sample Module 25
address_offset : 0x218 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT25 EADC_DAT25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT26 (DAT26)

EADC Data Register 26 for Sample Module 26
address_offset : 0x21C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT26 EADC_DAT26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL19 (SCTL19)

EADC Sample Module 19 Control Register
address_offset : 0x220 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL19 EADC_SCTL19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSEL INTPOS TRGDLYDIV TRGDLYCNT TRGSEL EXTREN EXTFEN EXTSMPT

CHSEL : EADC Sample Module Channel Selection
bits : 0 - 4 (5 bit)
access : read-write

INTPOS : Interrupt Flag Position Select
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC end of conversion

#1 : 1

Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC start of conversion

End of enumeration elements list.

TRGDLYDIV : EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection Trigger delay clock frequency:
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

EADC_CLK/1

#01 : 1

EADC_CLK/2

#10 : 2

EADC_CLK/4

#11 : 3

EADC_CLK/16

End of enumeration elements list.

TRGDLYCNT : EADC Sample Module Start of Conversion Trigger Delay Time
bits : 8 - 15 (8 bit)
access : read-write

TRGSEL : EADC Sample Module Start of Conversion Trigger Source Selection
bits : 16 - 20 (5 bit)
access : read-write

EXTREN : EADC External Trigger Rising Edge Enable Bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Rising edge Disabled when EADC selects EADC0_ST as trigger source

#1 : 1

Rising edge Enabled when EADC selects EADC0_ST as trigger source

End of enumeration elements list.

EXTFEN : EADC External Trigger Falling Edge Enable Bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Falling edge Disabled when EADC selects EADC0_ST as trigger source

#1 : 1

Falling edge Enabled when EADC selects EADC0_ST as trigger source

End of enumeration elements list.

EXTSMPT : EADC Sampling Time Extend When EADC is converting at high conversion rate, the sampling time of analog input voltage may not be enough if input channel loading is heavy, and software can extend EADC sampling time after trigger source is coming to get enough sampling time. The range of start delay time is from 0~255 EADC clock.
bits : 24 - 31 (8 bit)
access : read-write


EADC_SCTL20 (SCTL20)

EADC Sample Module 20 Control Register
address_offset : 0x224 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL20 EADC_SCTL20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL21 (SCTL21)

EADC Sample Module 21 Control Register
address_offset : 0x228 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL21 EADC_SCTL21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL22 (SCTL22)

EADC Sample Module 22 Control Register
address_offset : 0x22C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL22 EADC_SCTL22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL23 (SCTL23)

EADC Sample Module 23 Control Register
address_offset : 0x230 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL23 EADC_SCTL23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL24 (SCTL24)

EADC Sample Module 24 Control Register
address_offset : 0x234 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL24 EADC_SCTL24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTSMPT

EXTSMPT : EADC Sampling Time Extend When EADC is converting at high conversion rate, the sampling time of analog input voltage may not be enough if input channel loading is heavy, and software can extend EADC sampling time after trigger source is coming to get enough sampling time. The range of start delay time is from 0~255 EADC clock.
bits : 24 - 31 (8 bit)
access : read-write


EADC_SCTL25 (SCTL25)

EADC Sample Module 25 Control Register
address_offset : 0x238 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL25 EADC_SCTL25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL26 (SCTL26)

EADC Sample Module 26 Control Register
address_offset : 0x23C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL26 EADC_SCTL26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT9 (DAT9)

EADC Data Register 9 for Sample Module 9
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT9 EADC_DAT9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT10 (DAT10)

EADC Data Register 10 for Sample Module 10
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT10 EADC_DAT10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT11 (DAT11)

EADC Data Register 11 for Sample Module 11
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT11 EADC_DAT11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT12 (DAT12)

EADC Data Register 12 for Sample Module 12
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT12 EADC_DAT12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT13 (DAT13)

EADC Data Register 13 for Sample Module 13
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT13 EADC_DAT13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT14 (DAT14)

EADC Data Register 14 for Sample Module 14
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT14 EADC_DAT14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT15 (DAT15)

EADC Data Register 15 for Sample Module 15
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT15 EADC_DAT15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT1 (DAT1)

EADC Data Register 1 for Sample Module 1
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT1 EADC_DAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT16 (DAT16)

EADC Data Register 16 for Sample Module 16
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT16 EADC_DAT16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT17 (DAT17)

EADC Data Register 17 for Sample Module 17
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT17 EADC_DAT17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT18 (DAT18)

EADC Data Register 18 for Sample Module 18
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT18 EADC_DAT18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_CURDAT (CURDAT)

EADC PDMA Current Transfer Data Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EADC_CURDAT EADC_CURDAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURDAT

CURDAT : EADC PDMA Current Transfer Data (Read Only)
bits : 0 - 26 (27 bit)
access : read-only


EADC_CTL (CTL)

EADC Control Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_CTL EADC_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCEN ADCRST ADCIEN0 ADCIEN1 ADCIEN2 ADCIEN3 DIFFEN

ADCEN : EADC Converter Enable Bit Note: Before starting EADC conversion function, this bit should be set to 1. Clear it to 0 to disable EADC converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

EADC Disabled

#1 : 1

EADC Enabled

End of enumeration elements list.

ADCRST : EADC Converter Control Circuits Reset Note: EADCRST bit remains 1 during EADC reset, when EADC reset end, the EADCRST bit is automatically cleared to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Cause EADC control circuits reset to initial state, but not change the EADC registers value

End of enumeration elements list.

ADCIEN0 : Specific Sample Module EADC ADINT0 Interrupt Enable Bit The EADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module EADC conversion. If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Specific sample module EADC ADINT0 interrupt function Disabled

#1 : 1

Specific sample module EADC ADINT0 interrupt function Enabled

End of enumeration elements list.

ADCIEN1 : Specific Sample Module EADC ADINT1 Interrupt Enable Bit The EADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module EADC conversion. If EADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Specific sample module EADC ADINT1 interrupt function Disabled

#1 : 1

Specific sample module EADC ADINT1 interrupt function Enabled

End of enumeration elements list.

ADCIEN2 : Specific Sample Module EADC ADINT2 Interrupt Enable Bit The EADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module EADC conversion. If EADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Specific sample module EADC ADINT2 interrupt function Disabled

#1 : 1

Specific sample module EADC ADINT2 interrupt function Enabled

End of enumeration elements list.

ADCIEN3 : Specific Sample Module EADC ADINT3 Interrupt Enable Bit The EADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module EADC conversion. If EADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Specific sample module EADC ADINT3 interrupt function Disabled

#1 : 1

Specific sample module EADC ADINT3 interrupt function Enabled

End of enumeration elements list.

DIFFEN : Differential Analog Input Mode Enable Bit Note: In the differential mode, the input channel pair must be configured to EADC_CH15, EADC_CH14
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Single-end analog input mode

#1 : 1

Differential analog input mode

End of enumeration elements list.


EADC_SWTRG (SWTRG)

EADC Sample Module Software Start Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EADC_SWTRG EADC_SWTRG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRG

SWTRG : EADC Sample Module 0~26 Software Force to Start EADC Conversion Note: After writing this register to start EADC conversion, the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
bits : 0 - 26 (27 bit)
access : write-only

Enumeration:

0 : 0

No effect

1 : 1

Cause an EADC conversion when the priority is given to sample module

End of enumeration elements list.


EADC_PENDSTS (PENDSTS)

EADC Start of Conversion Pending Flag Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_PENDSTS EADC_PENDSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STPF

STPF : EADC Sample Module 0~26 Start of Conversion Pending Flag Read Operation:
bits : 0 - 26 (27 bit)
access : read-write

Enumeration:

0 : 0

There is no pending conversion for sample module

1 : 1

Sample module EADC start of conversion is pending. Clear pending flag cancel the conversion for sample module

End of enumeration elements list.


EADC_OVSTS (OVSTS)

EADC Sample Module Start of Conversion Overrun Flag Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_OVSTS EADC_OVSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPOVF

SPOVF : EADC SAMPLE0~26 Overrun Flag Note: This bit is cleared by writing 1 to it.
bits : 0 - 26 (27 bit)
access : read-write

Enumeration:

0 : 0

No sample module event overrun

1 : 1

Indicates a new sample module event is generated while an old one event is pending

End of enumeration elements list.


EADC_CTL1 (CTL1)

EADC Control1 Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_CTL1 EADC_CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRECHEN DISCHEN FDETCHEN ULPEN ULPDIV DECSET OSR

PRECHEN : Precharge Enable Note: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enabled.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel precharge Disabled

#1 : 1

Channel precharge Enabled

End of enumeration elements list.

DISCHEN : Discharge Enable Note: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enabled.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel discharge Disabled

#1 : 1

Channel discharge Enabled

End of enumeration elements list.

FDETCHEN : Floating Detect Channel Enable Bit Note: if FDETCHEN is enabled, internal floating detect channel is always turn on.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Floating Detect Channel Disabled

#1 : 1

Floating Detect Channel Enabled

End of enumeration elements list.

ULPEN : Ultra Low Power Mode Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Ultra low power mode Disabled

#1 : 1

Ultra low power mode Enabled

End of enumeration elements list.

ULPDIV : Ultra Low Power Mode Prescalar selection
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

#000 : 0

ADC_CLK divided by 1

#001 : 1

ADC_CLK divided by 2

#010 : 2

ADC_CLK divided by 4

#011 : 3

ADC_CLK divided by 8

#100 : 4

ADC_CLK divided by 16

End of enumeration elements list.

DECSET : High Speed Oversampling Mode Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

High speed oversampling mode Disabled

#1 : 1

High speed oversampling mode Enabled

End of enumeration elements list.

OSR : Repeat Conversion Times Select Note: The other steps of selection not listed above follow the same rule.
bits : 24 - 31 (8 bit)
access : read-write


EADC_DAT2 (DAT2)

EADC Data Register 2 for Sample Module 2
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT2 EADC_DAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL0 (SCTL0)

EADC Sample Module 0 Control Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL0 EADC_SCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSEL INTPOS TRGDLYDIV TRGDLYCNT TRGSEL EXTREN EXTFEN DBMEN EXTSMPT

CHSEL : EADC Sample Module Channel Selection
bits : 0 - 4 (5 bit)
access : read-write

INTPOS : Interrupt Flag Position Select
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC end of conversion

#1 : 1

Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC start of conversion

End of enumeration elements list.

TRGDLYDIV : EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection Trigger delay clock frequency:
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

EADC_CLK/1

#01 : 1

EADC_CLK/2

#10 : 2

EADC_CLK/4

#11 : 3

EADC_CLK/16

End of enumeration elements list.

TRGDLYCNT : EADC Sample Module Start of Conversion Trigger Delay Time
bits : 8 - 15 (8 bit)
access : read-write

TRGSEL : EADC Sample Module Start of Conversion Trigger Source Selection
bits : 16 - 20 (5 bit)
access : read-write

EXTREN : EADC External Trigger Rising Edge Enable Bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Rising edge Disabled when EADC selects EADC0_ST as trigger source

#1 : 1

Rising edge Enabled when EADC selects EADC0_ST as trigger source

End of enumeration elements list.

EXTFEN : EADC External Trigger Falling Edge Enable Bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Falling edge Disabled when EADC selects EADC0_ST as trigger source

#1 : 1

Falling edge Enabled when EADC selects EADC0_ST as trigger source

End of enumeration elements list.

DBMEN : Double Buffer Mode Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample has one sample result register (default)

#1 : 1

Sample has two sample result registers

End of enumeration elements list.

EXTSMPT : EADC Sampling Time Extend When EADC convertes at high conversion rate, the sampling time of analog input voltage may not be enough if input channel loading is heavy, and user can extend EADC sampling time after trigger source is coming to get enough sampling time. The range of start delay time is from 0~255 EADC clock.
bits : 24 - 31 (8 bit)
access : read-write


EADC_SCTL1 (SCTL1)

EADC Sample Module 1 Control Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL1 EADC_SCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL2 (SCTL2)

EADC Sample Module 2 Control Register
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL2 EADC_SCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL3 (SCTL3)

EADC Sample Module 3 Control Register
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL3 EADC_SCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL4 (SCTL4)

EADC Sample Module 4 Control Register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL4 EADC_SCTL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSEL INTPOS TRGDLYDIV TRGDLYCNT TRGSEL EXTREN EXTFEN EXTSMPT

CHSEL : EADC Sample Module Channel Selection
bits : 0 - 4 (5 bit)
access : read-write

INTPOS : Interrupt Flag Position Select
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC end of conversion

#1 : 1

Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC start of conversion

End of enumeration elements list.

TRGDLYDIV : EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection Trigger delay clock frequency:
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

EADC_CLK/1

#01 : 1

EADC_CLK/2

#10 : 2

EADC_CLK/4

#11 : 3

EADC_CLK/16

End of enumeration elements list.

TRGDLYCNT : EADC Sample Module Start of Conversion Trigger Delay Time
bits : 8 - 15 (8 bit)
access : read-write

TRGSEL : EADC Sample Module Start of Conversion Trigger Source Selection
bits : 16 - 20 (5 bit)
access : read-write

EXTREN : EADC External Trigger Rising Edge Enable Bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Rising edge Disabled when EADC selects EADC0_ST as trigger source

#1 : 1

Rising edge Enabled when EADC selects EADC0_ST as trigger source

End of enumeration elements list.

EXTFEN : EADC External Trigger Falling Edge Enable Bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Falling edge Disabled when EADC selects EADC0_ST as trigger source

#1 : 1

Falling edge Enabled when EADC selects EADC0_ST as trigger source

End of enumeration elements list.

EXTSMPT : EADC Sampling Time Extend When EADC is converting at high conversion rate, the sampling time of analog input voltage may not be enough if input channel loading is heavy, and software can extend EADC sampling time after trigger source is coming to get enough sampling time. The range of start delay time is from 0~255 EADC clock.
bits : 24 - 31 (8 bit)
access : read-write


EADC_SCTL5 (SCTL5)

EADC Sample Module 5 Control Register
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL5 EADC_SCTL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL6 (SCTL6)

EADC Sample Module 6 Control Register
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL6 EADC_SCTL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL7 (SCTL7)

EADC Sample Module 7 Control Register
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL7 EADC_SCTL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL8 (SCTL8)

EADC Sample Module 8 Control Register
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL8 EADC_SCTL8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL9 (SCTL9)

EADC Sample Module 9 Control Register
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL9 EADC_SCTL9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL10 (SCTL10)

EADC Sample Module 10 Control Register
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL10 EADC_SCTL10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL11 (SCTL11)

EADC Sample Module 11 Control Register
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL11 EADC_SCTL11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL12 (SCTL12)

EADC Sample Module 12 Control Register
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL12 EADC_SCTL12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL13 (SCTL13)

EADC Sample Module 13 Control Register
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL13 EADC_SCTL13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL14 (SCTL14)

EADC Sample Module 14 Control Register
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL14 EADC_SCTL14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL15 (SCTL15)

EADC Sample Module 15 Control Register
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL15 EADC_SCTL15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_DAT3 (DAT3)

EADC Data Register 3 for Sample Module 3
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_DAT3 EADC_DAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL16 (SCTL16)

EADC Sample Module 16 Control Register
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL16 EADC_SCTL16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL17 (SCTL17)

EADC Sample Module 17 Control Register
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL17 EADC_SCTL17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_SCTL18 (SCTL18)

EADC Sample Module 18 Control Register
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_SCTL18 EADC_SCTL18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_INTSRC0 (INTSRC0)

EADC Interrupt 0 Source Enable Control Register.
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_INTSRC0 EADC_INTSRC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPLIE0 SPLIE1 SPLIE2 SPLIE3 SPLIE4 SPLIE5 SPLIE6 SPLIE7 SPLIE8 SPLIE9 SPLIE10 SPLIE11 SPLIE12 SPLIE13 SPLIE14 SPLIE15 SPLIE16 SPLIE17 SPLIE18 SPLIE19 SPLIE20 SPLIE21 SPLIE22 SPLIE23 SPLIE24 SPLIE25 SPLIE26

SPLIE0 : Sample Module 0 Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 0 interrupt Disabled

#1 : 1

Sample Module 0 interrupt Enabled

End of enumeration elements list.

SPLIE1 : Sample Module 1 Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 1 interrupt Disabled

#1 : 1

Sample Module 1 interrupt Enabled

End of enumeration elements list.

SPLIE2 : Sample Module 2 Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 2 interrupt Disabled

#1 : 1

Sample Module 2 interrupt Enabled

End of enumeration elements list.

SPLIE3 : Sample Module 3 Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 3 interrupt Disabled

#1 : 1

Sample Module 3 interrupt Enabled

End of enumeration elements list.

SPLIE4 : Sample Module 4 Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 4 interrupt Disabled

#1 : 1

Sample Module 4 interrupt Enabled

End of enumeration elements list.

SPLIE5 : Sample Module 5 Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 5 interrupt Disabled

#1 : 1

Sample Module 5 interrupt Enabled

End of enumeration elements list.

SPLIE6 : Sample Module 6 Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 6 interrupt Disabled

#1 : 1

Sample Module 6 interrupt Enabled

End of enumeration elements list.

SPLIE7 : Sample Module 7 Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 7 interrupt Disabled

#1 : 1

Sample Module 7 interrupt Enabled

End of enumeration elements list.

SPLIE8 : Sample Module 8 Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 8 interrupt Disabled

#1 : 1

Sample Module 8 interrupt Enabled

End of enumeration elements list.

SPLIE9 : Sample Module 9 Interrupt Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 9 interrupt Disabled

#1 : 1

Sample Module 9 interrupt Enabled

End of enumeration elements list.

SPLIE10 : Sample Module 10 Interrupt Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 10 interrupt Disabled

#1 : 1

Sample Module 10 interrupt Enabled

End of enumeration elements list.

SPLIE11 : Sample Module 11 Interrupt Enable Bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 11 interrupt Disabled

#1 : 1

Sample Module 11 interrupt Enabled

End of enumeration elements list.

SPLIE12 : Sample Module 12 Interrupt Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 12 interrupt Disabled

#1 : 1

Sample Module 12 interrupt Enabled

End of enumeration elements list.

SPLIE13 : Sample Module 13 Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 13 interrupt Disabled

#1 : 1

Sample Module 13 interrupt Enabled

End of enumeration elements list.

SPLIE14 : Sample Module 14 Interrupt Enable Bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 14 interrupt Disabled

#1 : 1

Sample Module 14 interrupt Enabled

End of enumeration elements list.

SPLIE15 : Sample Module 15 Interrupt Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 15 interrupt Disabled

#1 : 1

Sample Module 15 interrupt Enabled

End of enumeration elements list.

SPLIE16 : Sample Module 16 Interrupt Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 16 interrupt Disabled

#1 : 1

Sample Module 16 interrupt Enabled

End of enumeration elements list.

SPLIE17 : Sample Module 17 Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 17 interrupt Disabled

#1 : 1

Sample Module 17 interrupt Enabled

End of enumeration elements list.

SPLIE18 : Sample Module 18 Interrupt Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 18 interrupt Disabled

#1 : 1

Sample Module 18 interrupt Enabled

End of enumeration elements list.

SPLIE19 : Sample Module 19 Interrupt Enable Bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 19 interrupt Disabled

#1 : 1

Sample Module 19 interrupt Enabled

End of enumeration elements list.

SPLIE20 : Sample Module 20 Interrupt Enable Bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 20 interrupt Disabled

#1 : 1

Sample Module 20 interrupt Enabled

End of enumeration elements list.

SPLIE21 : Sample Module 21 Interrupt Enable Bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 21 interrupt Disabled

#1 : 1

Sample Module 21 interrupt Enabled

End of enumeration elements list.

SPLIE22 : Sample Module 22 Interrupt Enable Bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 22 interrupt Disabled

#1 : 1

Sample Module 22 interrupt Enabled

End of enumeration elements list.

SPLIE23 : Sample Module 23 Interrupt Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 23 interrupt Disabled

#1 : 1

Sample Module 23 interrupt Enabled

End of enumeration elements list.

SPLIE24 : Sample Module 24 Interrupt Enable Bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 24 interrupt Disabled

#1 : 1

Sample Module 24 interrupt Enabled

End of enumeration elements list.

SPLIE25 : Sample Module 25 Interrupt Enable Bit
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 25 interrupt Disabled

#1 : 1

Sample Module 25 interrupt Enabled

End of enumeration elements list.

SPLIE26 : Sample Module 26 Interrupt Enable Bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sample Module 26 interrupt Disabled

#1 : 1

Sample Module 26 interrupt Enabled

End of enumeration elements list.


EADC_INTSRC1 (INTSRC1)

EADC Interrupt 1 Source Enable Control Register.
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_INTSRC1 EADC_INTSRC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_INTSRC2 (INTSRC2)

EADC Interrupt 2 Source Enable Control Register.
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_INTSRC2 EADC_INTSRC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_INTSRC3 (INTSRC3)

EADC Interrupt 3 Source Enable Control Register.
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_INTSRC3 EADC_INTSRC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_CMP0 (CMP0)

EADC Result Compare Register 0
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_CMP0 EADC_CMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCMPEN ADCMPIE CMPCOND CMPSPL CMPMCNT CMPWEN CMPDAT

ADCMPEN : EADC Result Compare Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Compare Disabled

#1 : 1

Compare Enabled

End of enumeration elements list.

ADCMPIE : EADC Result Compare Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Compare function interrupt Disabled

#1 : 1

Compare function interrupt Enabled

End of enumeration elements list.

CMPCOND : Compare Condition
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Set the compare condition as that when a 12-bit EADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one

#1 : 1

Set the compare condition as that when a 12-bit EADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one

End of enumeration elements list.

CMPSPL : Compare Sample Module Selection
bits : 3 - 7 (5 bit)
access : read-write

Enumeration:

#00000 : 0

Sample Module 0 conversion result EADC_DAT0 is selected to be compared

#00001 : 1

Sample Module 1 conversion result EADC_DAT1 is selected to be compared

#00010 : 2

Sample Module 2 conversion result EADC_DAT2 is selected to be compared

#00011 : 3

Sample Module 3 conversion result EADC_DAT3 is selected to be compared

#00100 : 4

Sample Module 4 conversion result EADC_DAT4 is selected to be compared

#00101 : 5

Sample Module 5 conversion result EADC_DAT5 is selected to be compared

#00110 : 6

Sample Module 6 conversion result EADC_DAT6 is selected to be compared

#00111 : 7

Sample Module 7 conversion result EADC_DAT7 is selected to be compared

#01000 : 8

Sample Module 8 conversion result EADC_DAT8 is selected to be compared

#01001 : 9

Sample Module 9 conversion result EADC_DAT9 is selected to be compared

#01010 : 10

Sample Module 10 conversion result EADC_DAT10 is selected to be compared

#01011 : 11

Sample Module 11 conversion result EADC_DAT11 is selected to be compared

#01100 : 12

Sample Module 12 conversion result EADC_DAT12 is selected to be compared

#01101 : 13

Sample Module 13 conversion result EADC_DAT13 is selected to be compared

#01110 : 14

Sample Module 14 conversion result EADC_DAT14 is selected to be compared

#01111 : 15

Sample Module 15 conversion result EADC_DAT15 is selected to be compared

#10000 : 16

Sample Module 16 conversion result EADC_DAT16 is selected to be compared

#10001 : 17

Sample Module 17 conversion result EADC_DAT17 is selected to be compared

#10010 : 18

Sample Module 18 conversion result EADC_DAT18 is selected to be compared

#10011 : 19

Sample Module 19 conversion result EADC_DAT19 is selected to be compared

#10100 : 20

Sample Module 20 conversion result EADC_DAT20 is selected to be compared

#10101 : 21

Sample Module 21 conversion result EADC_DAT21 is selected to be compared

#10110 : 22

Sample Module 22 conversion result EADC_DAT22 is selected to be compared

#10111 : 23

Sample Module 23 conversion result EADC_DAT23 is selected to be compared

#11000 : 24

Sample Module 24 conversion result EADC_DAT24 is selected to be compared

#11001 : 25

Sample Module 25 conversion result EADC_DAT25 is selected to be compared

#11010 : 26

Sample Module 26 conversion result EADC_DAT26 is selected to be compared

End of enumeration elements list.

CMPMCNT : Compare Match Count
bits : 8 - 11 (4 bit)
access : read-write

CMPWEN : Compare Window Mode Enable Bit Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

EADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched. EADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched

#1 : 1

EADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. EADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched

End of enumeration elements list.

CMPDAT : Comparison Data The 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
bits : 16 - 27 (12 bit)
access : read-write


EADC_CMP1 (CMP1)

EADC Result Compare Register 1
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_CMP1 EADC_CMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_CMP2 (CMP2)

EADC Result Compare Register 2
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_CMP2 EADC_CMP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_CMP3 (CMP3)

EADC Result Compare Register 3
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_CMP3 EADC_CMP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EADC_STATUS0 (STATUS0)

EADC Status Register 0
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EADC_STATUS0 EADC_STATUS0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALID OV

VALID : EADC_DAT0~15 Data Valid Flag
bits : 0 - 15 (16 bit)
access : read-only

OV : EADC_DAT0~15 Overrun Flag
bits : 16 - 31 (16 bit)
access : read-only


EADC_STATUS1 (STATUS1)

EADC Status Register 1
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EADC_STATUS1 EADC_STATUS1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALID OV

VALID : EADC_DAT16~26 Data Valid Flag
bits : 0 - 10 (11 bit)
access : read-only

OV : EADC_DAT16~26 Overrun Flag
bits : 16 - 26 (11 bit)
access : read-only


EADC_STATUS2 (STATUS2)

EADC Status Register 2
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_STATUS2 EADC_STATUS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADIF0 ADIF1 ADIF2 ADIF3 ADCMPF0 ADCMPF1 ADCMPF2 ADCMPF3 ADOVIF0 ADOVIF1 ADOVIF2 ADOVIF3 ADCMPO0 ADCMPO1 ADCMPO2 ADCMPO3 CHANNEL BUSY ADOVIF STOVF AVALID AOV

ADIF0 : EADC ADINT0 Interrupt Flag Note 1: This bit is cleared by writing 1 to it. Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No ADINT0 interrupt pulse received

#1 : 1

ADINT0 interrupt pulse has been received

End of enumeration elements list.

ADIF1 : EADC ADINT1 Interrupt Flag Note 1: This bit is cleared by writing 1 to it. Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No ADINT1 interrupt pulse received

#1 : 1

ADINT1 interrupt pulse has been received

End of enumeration elements list.

ADIF2 : EADC ADINT2 Interrupt Flag Note 1: This bit is cleared by writing 1 to it. Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No ADINT2 interrupt pulse received

#1 : 1

ADINT2 interrupt pulse has been received

End of enumeration elements list.

ADIF3 : EADC ADINT3 Interrupt Flag Note 1: This bit is cleared by writing 1 to it. Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No ADINT3 interrupt pulse received

#1 : 1

ADINT3 interrupt pulse has been received

End of enumeration elements list.

ADCMPF0 : EADC Compare 0 Flag When the specific sample module EADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. Note: This bit is cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion result in EADC_DAT does not meet EADC_CMP0 register setting

#1 : 1

Conversion result in EADC_DAT meets EADC_CMP0 register setting

End of enumeration elements list.

ADCMPF1 : EADC Compare 1 Flag When the specific sample module EADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. Note: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion result in EADC_DAT does not meet EADC_CMP1 register setting

#1 : 1

Conversion result in EADC_DAT meets EADC_CMP1 register setting

End of enumeration elements list.

ADCMPF2 : EADC Compare 2 Flag When the specific sample module EADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. Note: This bit is cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion result in EADC_DAT does not meet EADC_CMP2 register setting

#1 : 1

Conversion result in EADC_DAT meets EADC_CMP2 register setting

End of enumeration elements list.

ADCMPF3 : EADC Compare 3 Flag When the specific sample module EADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. Note: This bit is cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion result in EADC_DAT does not meet EADC_CMP3 register setting

#1 : 1

Conversion result in EADC_DAT meets EADC_CMP3 register setting

End of enumeration elements list.

ADOVIF0 : EADC ADINT0 Interrupt Flag Overrun Note: This bit is cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADINT0 interrupt flag is not overwritten to 1

#1 : 1

ADINT0 interrupt flag is overwritten to 1

End of enumeration elements list.

ADOVIF1 : EADC ADINT1 Interrupt Flag Overrun Note: This bit is cleared by writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADINT1 interrupt flag is not overwritten to 1

#1 : 1

ADINT1 interrupt flag is overwritten to 1

End of enumeration elements list.

ADOVIF2 : EADC ADINT2 Interrupt Flag Overrun Note: This bit is cleared by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADINT2 interrupt flag is not overwritten to 1

#1 : 1

ADINT2 interrupt flag is s overwritten to 1

End of enumeration elements list.

ADOVIF3 : EADC ADINT3 Interrupt Flag Overrun Note: This bit is cleared by writing 1 to it.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADINT3 interrupt flag is not overwritten to 1

#1 : 1

ADINT3 interrupt flag is overwritten to 1

End of enumeration elements list.

ADCMPO0 : EADC Compare 0 Output Status (Read Only) The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

#0 : 0

Conversion result in EADC_DAT less than CMPDAT0 setting

#1 : 1

Conversion result in EADC_DAT great than or equal CMPDAT0 setting

End of enumeration elements list.

ADCMPO1 : EADC Compare 1 Output Status (Read Only) The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

#0 : 0

Conversion result in EADC_DAT less than CMPDAT1 setting

#1 : 1

Conversion result in EADC_DAT great than or equal to CMPDAT1 setting

End of enumeration elements list.

ADCMPO2 : EADC Compare 2 Output Status (Read Only) The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

#0 : 0

Conversion result in EADC_DAT less than CMPDAT2 setting

#1 : 1

Conversion result in EADC_DAT great than or equal to CMPDAT2 setting

End of enumeration elements list.

ADCMPO3 : EADC Compare 3 Output Status (Read Only) The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#0 : 0

Conversion result in EADC_DAT less than CMPDAT3 setting

#1 : 1

Conversion result in EADC_DAT great than or equal to CMPDAT3 setting

End of enumeration elements list.

CHANNEL : Current Conversion Channel (Read Only)
bits : 16 - 20 (5 bit)
access : read-only

BUSY : Busy/Idle (Read Only) Note: this flag will be high after 4*EADC_CLK cycles, when the trigger source is coming.
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

#0 : 0

EADC is in idle state

#1 : 1

EADC is busy at conversion

End of enumeration elements list.

ADOVIF : All EADC Interrupt Flag Overrun Bits Check (Read Only) Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

#0 : 0

None of ADINT interrupt flag ADOVIFn, n=0~3 is overwritten to 1

#1 : 1

Any one of ADINT interrupt flag ADOVIFn, n=0~3 is overwritten to 1

End of enumeration elements list.

STOVF : for All EADC Sample Module Start of Conversion Overrun Flags Check (Read Only) Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

#0 : 0

None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1

#1 : 1

Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1

End of enumeration elements list.

AVALID : for All Sample Module EADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only) Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
bits : 26 - 26 (1 bit)
access : read-only

Enumeration:

#0 : 0

None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1

#1 : 1

Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1

End of enumeration elements list.

AOV : for All Sample Module EADC Result Data Register Overrun Flags Check (Read Only) Note: This bit will keep 1 when any OVn Flag is equal to 1.
bits : 27 - 27 (1 bit)
access : read-only

Enumeration:

#0 : 0

None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1

#1 : 1

Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1

End of enumeration elements list.


EADC_STATUS3 (STATUS3)

EADC Status Register 3
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EADC_STATUS3 EADC_STATUS3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURSPL

CURSPL : EADC Current Sample Module (Read Only) This register shows the current EADC is controlled by which sample module control logic modules. If the EADC is Idle, the bit filed will set to 0x1F.
bits : 0 - 4 (5 bit)
access : read-only


EADC_VREF (VREF)

EADC Reference Voltage Control Register
address_offset : 0xFF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADC_VREF EADC_VREF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFSEL

REFSEL : Positive Reference Voltage Source Selection
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Positive Reference Voltage Source from AVDD

#1 : 1

Positive Reference Voltage Source from VREFP

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.