\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
DAC0 Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACEN : DAC Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC Disabled
#1 : 1
DAC Enabled
End of enumeration elements list.
DACIEN : DAC Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC interrupt Disabled
#1 : 1
DAC interrupt Enabled
End of enumeration elements list.
DMAEN : DMA Mode Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA mode Disabled
#1 : 1
DMA mode Enabled
End of enumeration elements list.
DMAURIEN : DMA Under-run Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA under-run interrupt Disabled
#1 : 1
DMA under-run interrupt Enabled
End of enumeration elements list.
TRGEN : Trigger Mode Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC event trigger mode Disabled
#1 : 1
DAC event trigger mode Enabled
End of enumeration elements list.
TRGSEL : Trigger Source Selection
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 0
Software trigger
#001 : 1
External pin DAC0_ST trigger
#010 : 2
Timer 0 trigger
#011 : 3
Timer 1 trigger
#100 : 4
Timer 2 trigger
#101 : 5
Timer 3 trigger
#110 : 6
EPWM0 trigger
#111 : 7
EPWM1 trigger
End of enumeration elements list.
ETRGSEL : External Pin Trigger Selection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Low level trigger
#01 : 1
High level trigger
#10 : 2
Falling edge trigger
#11 : 3
Rising edge trigger
End of enumeration elements list.
DAC0 Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FINISH : DAC Conversion Complete Finish Flag
Note: This bit is set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC is in conversion state
#1 : 1
DAC conversion finish
End of enumeration elements list.
DMAUDR : DMA Under-run Interrupt Flag
Note: User writes 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No DMA under-run error condition occurred
#1 : 1
DMA under-run error condition occurred
End of enumeration elements list.
BUSY : DAC Busy Flag (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
DAC is ready for next conversion
#1 : 1
DAC is busy in conversion
End of enumeration elements list.
DAC0 Timing Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETTLET : DAC Output Settling Time
User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
For example, DAC controller clock speed is 80 MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50.
bits : 0 - 9 (10 bit)
access : read-write
DAC0 Reference Voltage Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELVREF : DAC Reference Voltage Selection
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC reference voltage is from AVDD
#1 : 1
DAC reference voltage is from VREFP
End of enumeration elements list.
OUTFLOAT : DAC Output Floating Selection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC_OUT output DAC_ROUT
#1 : 1
DAC_OUT output Hi-z
End of enumeration elements list.
DAC0 Software Trigger Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWTRG : Software Trigger
Note: User writes this bit to generate one shot pulse and this bit is cleared to 0 by hardware automatically reading this bit will always get 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger Disabled
#1 : 1
Software trigger Enabled
End of enumeration elements list.
DAC0 Data Holding Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACDAT : DAC 8-bit Holding Data
These bits are written by user software which specifies 8-bit conversion data for DAC output.
bits : 0 - 7 (8 bit)
access : read-write
DAC0 Data Output Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATOUT : DAC 8-bit Output Data
These bits are current digital data for DAC output conversion.
It is loaded from DAC_DAT register and user cannot write it directly.
bits : 0 - 11 (12 bit)
access : read-only
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