SYS_PDID (PDID)

SYS_WAIT (WAIT)

SYS_REGLCTL (REGLCTL)

SYS_TSOFFSET (TSOFFSET)

SYS_BODCTL (BODCTL)

SYS_IVSCTL (IVSCTL)

SYS_PORCTL (PORCTL)

SYS_GPA_MFP (GPA_MFP)

SYS_GPB_MFP (GPB_MFP)

SYS_GPC_MFP (GPC_MFP)

SYS_GPD_MFP (GPD_MFP)

SYS_RSTSTS (RSTSTS)

SYS_GPE_MFP (GPE_MFP)

SYS_GPF_MFP (GPF_MFP)

SYS_IPRST0 (IPRST0)

SYS_IPRST1 (IPRST1)

PDID : Part Device Identification Number (Read Only) This register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only

HCLKWS : HCLK Wait State Cycle Control Bit This bit is used to enable/disable HCLK wait state when access Flash. Note: When HCLK frequency is faster than 48M(60)Hz, insert one wait state is necessary.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REGLCTL : Register Lock Control Disable Index (Read Only) The Protected registers are: SYS_IPRST0 SYS_IPRST0 SYS_BODCTL LDOCR SYS_PORCTL CLK_PWRCTL CLK_APBCLK bit[0] CLK_CLKSEL0 CLK_CLKSEL1 bit[1:0] NMI_SEL bit[8] FMC_ISPCTL FMC_ISPTRG WDT_CTL Note: The bits which are write-protected will be noted as' (Write Protect)' beside the description.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REGPROTDIS : Register Write-protection Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. After this sequence is completed, the SYS_REGLCTL bit will be set to 1 and write-protection registers can be normal write.
bits : 1 - 7 (7 bit)
access : write-only

VTEMP25 :
bits : 0 - 7 (8 bit)
access : read-only

VTEMP125 :
bits : 8 - 15 (8 bit)
access : read-only

BGVAL : BGVAL
bits : 16 - 23 (8 bit)
access : read-only

BODEN : Brown-out Detector Enable Control (Write Protect) The default value is set by flash controller user configuration register CBODEN (CONFIG0 [11]). Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODVL : Brown-out Detector Threshold Voltage Selection (Write Protect) The default value is set by flash controller user configuration register CBOV (CONFIG0 [15:13]). Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRSTEN : Brown-out Reset Enable Control (Write Protect) The default value is set by flash controller user configuration register CBORST(CONFIG0[19]) bit . Note1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). BOD will wake CPU up when BODOUT is high in power-down mode. Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODIF : Brown-out Detector Interrupt Flag Note: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRLPM : Low Voltage Reset Low Power Mode (Write Protect) Note1: The LVR consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the LVR response. Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODOUT : Brown-out Detector Output Status
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVREN : Low Voltage Reset Enable Control (Write Protect) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VTEMPEN : Temperature Sensor Enable Control This bit is used to enable/disable temperature sensor function. Note: After this bit is set to 1, the value of temperature sensor output can be obtained from A/D conversion result. Please refer to ADC function chapter for details.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POROFF : Power-on Reset Enable Control (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write

PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PA1MFP : PA.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PA2MFP : PA.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PA3MFP : PA.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PA4MFP : PA.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PA5MFP : PA.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PA6MFP : PA.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PA7MFP : PA.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PC1MFP : PC.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PC2MFP : PC.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PC3MFP : PC.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PC4MFP : PC.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PC5MFP : PC.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PC6MFP : PC.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PC7MFP : PC.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PD1MFP : PD.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PD2MFP : PD.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PD3MFP : PD.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PD4MFP : PD.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PD5MFP : PD.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PD6MFP : PD.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PD7MFP : PD.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PORF : POR Reset Flag The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINRF : NRESET Pin Reset Flag The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRF : WDT Reset Flag The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. Note1: Write 1 to clear this bit to 0. Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRF : LVR Reset Flag The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRF : BOD Reset Flag The BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRF : System Reset Flag The system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURF : CPU Reset Flag The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC). Note: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HFAULTRF : Hard Fault Reset Flag Note: Write 1 to clear this bit to 0.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PE0MFP : PE.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PE1MFP : PE.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PE2MFP : PE.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PE3MFP : PE.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PE4MFP : PE.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PE5MFP : PE.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PE6MFP : PE.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PE7MFP : PE.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PF0MFP : PF.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PF1MFP : PF.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PF2MFP : PF.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PF3MFP : PF.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PF4MFP : PF.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

CHIPRST : Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURST : Processor Core One-shot Reset (Write Protect) Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GDMARST : GDMA One-shot Reset (Write Protect) Setting this bit will only reset the GDMA, and this bit will automatically return to 0 after the 2 clock cycles. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPRST : CAP Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPRST : OP Controller Reset
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWMRST : Basic PWM Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPWMRST : Enhanced PWM Controller Reset
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USCI1RST : USCI1 Controller Reset
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USCI2RST : USCI2 Controller Reset
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCRST : ADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMPRST : ACMP Controller Reset
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.