SYST_CTL

NVIC_ISER

SYST_RVR

SYST_CVR

NVIC_ICER

NVIC_ISPR

NVIC_ICPR

NVIC_IPR0

NVIC_IPR1

NVIC_IPR2

NVIC_IPR3

NVIC_IPR4

NVIC_IPR5

NVIC_IPR6

NVIC_IPR7

SCS_CPUID (CPUID)

SCS_ICSR (ICSR)

SCS_AIRCR (AIRCR)

SCS_SCR (SCR)

SCS_SHPR2 (SHPR2)

SCS_SHPR3 (SHPR3)

ENABLE : System Tick Counter Enable Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICKINT : System Tick Interrupt Enable Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSRC : System Tick Clock Source Select Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COUNTFLAG : System Tick Counter Flag Return 1 If Timer Counted to 0 Since Last Time this Register Was Read
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SETENA : Interrupt Enable Register Enable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Write operation: Read value indicates the current enable status.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RELOAD : System Tick Reload Value Value to load into the Current Value register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write

CURRENT : System Tick Current Value Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
bits : 0 - 23 (24 bit)
access : read-write

CLRENA : Interrupt Disable Register Disable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Write operation: Note: Read value indicates the current enable status.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SETPEND : Set Interrupt Pending Register Write operation: Note: Read value indicates the current pending status.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLRPEND : Clear Interrupt Pending Register Write operation: Note: Read value indicates the current pending status.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI0 : Priority of IRQ0 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI1 : Priority of IRQ1 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI2 : Priority of IRQ2 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI3 : Priority of IRQ3 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI4 : Priority of IRQ4 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI5 : Priority of IRQ5 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI6 : Priority of IRQ6 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI7 : Priority of IRQ7 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI8 : Priority of IRQ8 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI9 : Priority of IRQ9 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI10 : Priority of IRQ10 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI11 : Priority of IRQ11 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI12 : Priority of IRQ12 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI13 : Priority of IRQ13 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI14 : Priority of IRQ14 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI15 : Priority of IRQ15 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI16 : Priority of IRQ16 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI17 : Priority of IRQ17 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI18 : Priority of IRQ18 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI19 : Priority of IRQ19 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI20 : Priority of IRQ20 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI21 : Priority of IRQ21 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI22 : Priority of IRQ22 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI23 : Priority of IRQ23 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI24 : Priority of IRQ24 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI25 : Priority of IRQ25 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI26 : Priority of IRQ26 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI27 : Priority of IRQ27 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI28 : Priority of IRQ28 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI29 : Priority of IRQ29 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI30 : Priority of IRQ30 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI31 : Priority of IRQ31 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

REVISION : Revision Number Reads as 0x0
bits : 0 - 3 (4 bit)
access : read-only

PARTNO : Part Number of the Processor Reads as 0xC20.
bits : 4 - 15 (12 bit)
access : read-only

PART : Architecture of the Processor Reads as 0xC for ARMv6-M parts
bits : 16 - 19 (4 bit)
access : read-only

IMPLEMENTER : Implementer Code
bits : 24 - 31 (8 bit)
access : read-only

VECTACTIVE : Contains the Active Exception Number
bits : 0 - 8 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTPENDING : Exception Number of the Highest Priority Pending Enabled Exception
bits : 12 - 20 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRPENDING : Interrupt Pending Flag,Excluding NMI and Faults (Read Only)
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISRPREEMPT : Interrupt Preempt Bit(Read Only) If set, a pending exception will be serviced on exit from the debug halt state
bits : 23 - 23 (1 bit)
access : read-only

PENDSTCLR : SysTick Exception Clear-pending Bit Write Operation: Note: This bit is write-only. When you want to clear PENDST bit, you must 'write 0 toPENDSTSET and write 1 to PENDSTCLR' at the same time.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSTSET : SysTick Exception Set-pending Bit Write Operation:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSVCLR : PendSV Clear-pending Bit Write Operation: This bit is write-only. To clear the PENDSV bit, you must 'write 0 to PENDSVSET andwrite 1 to PENDSVCLR' at the same time.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSVSET : PendSV Set-pending Bit Write Operation: Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NMIPENDSET : NMI Set-pending Bit Write Operation: Note: Because NMI is the highest-priority exception, normally the processor entersthe NMI exception handler as soon as it detects a write of 1 to this bit. Entering thehandler then clears this bit to 0. This means a read of this bit by the NMI exceptionhandler returns 1 only if the NMI signal is reasserted while the processor is executingthat handler.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTCLRACTIVE : Exception Active Status Clear Bit Reserved for debug use. When writing to the register, user must write 0 to this bit, otherwise behavior is unpredictable.
bits : 1 - 1 (1 bit)
access : read-write

SYSRESETREQ : System Reset Request Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested. The bit is a write only bit and self-clears as part of the reset sequence.
bits : 2 - 2 (1 bit)
access : read-write

VECTORKEY : Register Access Key Write Operation: When writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status. Read Operation: Read as 0xFA05.
bits : 16 - 31 (16 bit)
access : read-write

SLEEPONEXIT : Sleep-on-exit Enable Control This bit indicates sleep-on-exit when returning from Handler mode to Thread mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLEEPDEEP : Processor Deep Sleep and Sleep Mode Selection Controls whether the processor uses sleep or deep sleep as its low power mode:
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEVONPEND : Send Event on Pending Bit When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI11 : Priority of System Handler 11 - SVCall '0' denotes the highest priority and '3' denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI14 : Priority of System Handler 14 - PendSV '0' denotes the highest priority and '3' denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI15 : Priority of System Handler 15 - SysTick '0' denotes the highest priority and '3' denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write