INT_NMICTL (NMICTL)

INT_IRQSTS (IRQSTS)

NMISEL : NMI Interrupt Source Selection The NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMTSEL.
bits : 0 - 4 (5 bit)
access : read-write

NMISELEN : NMI Interrupt Enable Control (Write Protected) Note: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IRQ : MCU IRQ Source Register The IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There is one mode to generate interrupt to Cortex-M0 - the normal mode. The IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0. When the IRQ[n] is 0, setting IRQ[n] to 1 will generate an interrupt to Cortex-M0 NVIC[n]. When the IRQ[n] is 1 (i.e. an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting IRQ[n] 0 has no effect.
bits : 0 - 31 (32 bit)
access : read-write