Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTCLKEN : External Clock Enable Control (Write Protect)
These two bits are default set to '00' and EXT_CLK(PC.3) pins are GPIO.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable external EXT_CLK
#01 : 1
Reserved.
#10 : 2
Reserved.
#11 : 3
Enable external EXT_CLK
End of enumeration elements list.
HIRCEN : HIRC Enable Control (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
48(60) MHz internal high speed RC oscillator (HIRC) Disabled
#1 : 1
48(60) MHz internal high speed RC oscillator (HIRC) Enabled
End of enumeration elements list.
LIRCEN : LIRC Enable Control (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
10 kHz internal low speed RC oscillator (LIRC) Disabled
#1 : 1
10 kHz internal low speed RC oscillator (LIRC) Enabled
End of enumeration elements list.
PDWKDLY : Wake-up Delay Counter Enable Control (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip works at external clock input(EXT_CLK), and 256 clock cycles when chip works at 48(60) MHz internal high speed RC oscillator (HIRC).
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock cycles delay Disabled
#1 : 1
Clock cycles delay Enabled
End of enumeration elements list.
PDWKIEN : Power-down Mode Wake-up Interrupt Enable Control (Write Protect)
Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down mode wake-up interrupt Disabled
#1 : 1
Power-down mode wake-up interrupt Enabled
End of enumeration elements list.
PDWKIF : Power-down Mode Wake-up Interrupt Status
Set by 'Power-down wake-up event', it indicates that resume from 'Power-down mode'
The flag is set if the GPIO, USCIx, WDT, ACMPx, BOD, TMRx wake-up occurred.
Note1: Write 1 to clear the bit to 0.
Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write
PDEN : System Power-down Enable Control (Write Protect)
When this bit is set to 1, Power-down mode is enabled.
When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.
In Power-down mode, EXT_CLK and HIRC will be disabled.
In Power-down mode, the system clocks are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode if the peripheral clock source is from LIRC. LIRC is controlled by bit LIRCEN.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip operating normally or chip in idle mode because of WFI/WFE command
#1 : 1
Chip enters Power-down mode when CPU sleep command WFI/WFE
End of enumeration elements list.
PDMODE : 00: LDO Off When Power Down Mode
01: LDO on when power down node
bits : 14 - 15 (2 bit)
access : read-write
HIRCSEL : 0: Internal High Speed RC Oscillator Clock Will Output 48MHz
1: Internal high speed RC oscillator clock will output 60MHz
bits : 24 - 24 (1 bit)
access : read-write
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKSEL : HCLK Clock Source Selection (Write Protect)
Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from EXT_CLK
#01 : 1
Clock source from LIRC
#10 : 2
Reserved.
#11 : 3
Clock source from HIRC
End of enumeration elements list.
STCLKSEL : Cortex-M0 SysTick Clock Source Selection (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from EXT_CLK
#01 : 1
Clock source from EXT_CLK/2
#10 : 2
Clock source from HCLK/2
#11 : 3
Clock source from HIRC/2
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTSEL : Watchdog Timer Clock Source Selection (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external clock input (EXT_CLK)
#01 : 1
Reserved.
#10 : 2
Clock source from HCLK0/2048
#11 : 3
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
End of enumeration elements list.
TMR0SEL : TIMER0 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external clock input (EXT_CLK)
#001 : 1
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from external clock T0 pin
#100 : 4
Clock source from 48(60) MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR1SEL : TIMER1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external clock input (EXT_CLK)
#001 : 1
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from external clock T1 pin
#100 : 4
Clock source from 48(60) MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR2SEL : TIMER2 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external clock input (EXT_CLK)
#001 : 1
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from external clock T2 pin
#100 : 4
Clock source from 48(60) MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
CLKOSEL : Clock Divider Clock Source Selection
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external clock input (EXT_CLK)
#01 : 1
Reserved.
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from 48(60) MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
Clock Divider Number Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPCKEN : Flash ISP Controller Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash ISP peripheral clock Disabled
#1 : 1
Flash ISP peripheral clock Enabled
End of enumeration elements list.
HDIVCKEN : Hardware Divider Controller Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
HDIV peripheral clock Disabled
#1 : 1
HDIV peripheral clock Enabled
End of enumeration elements list.
GDMACKEN : Gereral Direct Memory Access Controller Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
GDMA clock Disabled
#1 : 1
GDMA clock Enabled
End of enumeration elements list.
Clock Status Monitor Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REXCLKSTB : External Clock Source Stable Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
External clock is not stable or disabled
#1 : 1
External clock is stable and enabled
End of enumeration elements list.
LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled
#1 : 1
10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled
End of enumeration elements list.
HIRCSTB : HIRC Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
48(60) MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled
#1 : 1
48(60) MHz internal high speed RC oscillator (HIRC) clock is stable and enabled
End of enumeration elements list.
CLKSFAIL : Clock Switching Fail Flag (Read Only)
This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.
Note: Write 1 to clear the bit to 0.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock switching success
#1 : 1
Clock switching failure
End of enumeration elements list.
Clock Output Control Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Clock Output Frequency Selection
The formula of output frequency is
Fin is the input clock frequency.
Fout is the frequency of divider output clock.
N is the 4-bit value of FREQSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
CLKOEN : Clock Output Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output function Disabled
#1 : 1
Clock Output function Enabled
End of enumeration elements list.
DIV1EN : Clock Output Divide One Enable Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output will output clock with source frequency divided by FREQSEL
#1 : 1
Clock Output will output clock with source frequency
End of enumeration elements list.
APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTCKEN : Watchdog Timer Clock Enable Control (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer clock Disabled
#1 : 1
Watchdog timer clock Enabled
End of enumeration elements list.
TMR0CKEN : Timer0 Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 clock Disabled
#1 : 1
Timer0 clock Enabled
End of enumeration elements list.
TMR1CKEN : Timer1 Clock Enable Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 clock Disabled
#1 : 1
Timer1 clock Enabled
End of enumeration elements list.
TMR2CKEN : Timer2 Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 clock Disabled
#1 : 1
Timer2 clock Enabled
End of enumeration elements list.
CLKOCKEN : CLKO Clock Enable Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
CLKO clock Disabled
#1 : 1
CLKO clock Enabled
End of enumeration elements list.
ECAPCKEN : Input Capture Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAP clock Disabled
#1 : 1
CAP clock Enabled
End of enumeration elements list.
OPCKEN : OP Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
OP clock Disabled
#1 : 1
OP clock Enabled
End of enumeration elements list.
EPWMCKEN : Enhanced PWM Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM channel 0/1 clock Disabled
#1 : 1
EPWM channel 0/1 clock Enabled
End of enumeration elements list.
BPWMCKEN : Basic PWM Channel 0/1 Clock Enable Control
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
BBPWM channel 0/1 clock Disabled
#1 : 1
BPWM channel 0/1 clock Enabled
End of enumeration elements list.
USCI1CKEN : USCI1 Clock Enable Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI1 clock Disabled
#1 : 1
USCI1 clock Enabled
End of enumeration elements list.
USCI2CKEN : USCI2 Clock Enable Control
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI2 clock Disabled
#1 : 1
USCI2 clock Enabled
End of enumeration elements list.
ADCCKEN : Analog-digital-converter (ADC) Clock Enable Control
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC clock Disabled
#1 : 1
ADC clock Enabled
End of enumeration elements list.
ACMPCKEN : Analog Comparator Clock Enable Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog comparator clock Disabled
#1 : 1
Analog comparator clock Enabled
End of enumeration elements list.
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