PA_MODE

PA_PIN

PE_MODE

PE_DINOFF

PE_DOUT

PE_DATMSK

PE_PIN

PE_DBEN

PE_INTTYPE

PE_INTEN

PE_INTSRC

PE_SMTEN

PE_SLEWCTL

PE_PLEN

PE_PHEN

PA_DBEN

PF_MODE

PF_DINOFF

PF_DOUT

PF_DATMSK

PF_PIN

PF_DBEN

PF_INTTYPE

PF_INTEN

PF_INTSRC

PF_SMTEN

PF_SLEWCTL

PF_PLEN

PF_PHEN

PA_INTTYPE

PA_INTEN

PA_INTSRC

PA_SMTEN

PA_SLEWCTL

PA_PLEN

PA_PHEN

PA_DINOFF

PB_MODE

PB_DINOFF

GPIO_DBCTL (DBCTL)

PB_DOUT

PB_DATMSK

PB_PIN

PB_DBEN

PB_INTTYPE

PB_INTEN

PB_INTSRC

PB_SMTEN

PB_SLEWCTL

PB_PLEN

PB_PHEN

PA_DOUT

PC_MODE

PA0_PDIO

PA1_PDIO

PA2_PDIO

PA3_PDIO

PA4_PDIO

PA5_PDIO

PA6_PDIO

PA7_PDIO

PC_DINOFF

PB0_PDIO

PB1_PDIO

PB2_PDIO

PB3_PDIO

PB4_PDIO

PB5_PDIO

PB6_PDIO

PB7_PDIO

PC_DOUT

PC0_PDIO

PC1_PDIO

PC2_PDIO

PC3_PDIO

PC4_PDIO

PC5_PDIO

PC6_PDIO

PC7_PDIO

PC_DATMSK

PD1_PDIO

PD2_PDIO

PD3_PDIO

PD4_PDIO

PD5_PDIO

PD6_PDIO

PD7_PDIO

PC_PIN

PE0_PDIO

PE1_PDIO

PE2_PDIO

PE3_PDIO

PE4_PDIO

PE5_PDIO

PE6_PDIO

PE7_PDIO

PC_DBEN

PF0_PDIO

PF1_PDIO

PF2_PDIO

PF3_PDIO

PF4_PDIO

PC_INTTYPE

PC_INTEN

PC_INTSRC

PC_SMTEN

PC_SLEWCTL

PC_PLEN

PC_PHEN

PA_DATMSK

PD_MODE

PD_DINOFF

PD_DOUT

PD_DATMSK

PD_PIN

PD_DBEN

PD_INTTYPE

PD_INTEN

PD_INTSRC

PD_SMTEN

PD_SLEWCTL

PD_PLEN

PD_PHEN

MODE0 : Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE1 : Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE2 : Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE3 : Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE4 : Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE5 : Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE6 : Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE7 : Port A-F I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIN0 : Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note:
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note:
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note:
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note:
bits : 3 - 3 (1 bit)
access : read-only

PIN4 : Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note:
bits : 4 - 4 (1 bit)
access : read-only

PIN5 : Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note:
bits : 5 - 5 (1 bit)
access : read-only

PIN6 : Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note:
bits : 6 - 6 (1 bit)
access : read-only

PIN7 : Port A-F Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note:
bits : 7 - 7 (1 bit)
access : read-only

DBEN0 : Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN1 : Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN2 : Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN3 : Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN4 : Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN5 : Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN6 : Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN7 : Port A-F Pin[n] Input Signal De-bounce Enable Control The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE0 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE1 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE2 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE3 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE4 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE5 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE6 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE7 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN0 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN1 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN2 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN3 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN4 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN5 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN6 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN7 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN0 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN1 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN2 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN3 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN4 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN5 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN6 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN7 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC0 : Port A-F Pin[n] Interrupt Source Flag Write Operation :
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC1 : Port A-F Pin[n] Interrupt Source Flag Write Operation :
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC2 : Port A-F Pin[n] Interrupt Source Flag Write Operation :
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC3 : Port A-F Pin[n] Interrupt Source Flag Write Operation :
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC4 : Port A-F Pin[n] Interrupt Source Flag Write Operation :
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC5 : Port A-F Pin[n] Interrupt Source Flag Write Operation :
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC6 : Port A-F Pin[n] Interrupt Source Flag Write Operation :
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC7 : Port A-F Pin[n] Interrupt Source Flag Write Operation :
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN0 : Port A-F Pin[n] Input Schmitt Trigger Enable Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN1 : Port A-F Pin[n] Input Schmitt Trigger Enable Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN2 : Port A-F Pin[n] Input Schmitt Trigger Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN3 : Port A-F Pin[n] Input Schmitt Trigger Enable Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN4 : Port A-F Pin[n] Input Schmitt Trigger Enable Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN5 : Port A-F Pin[n] Input Schmitt Trigger Enable Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN6 : Port A-F Pin[n] Input Schmitt Trigger Enable Control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN7 : Port A-F Pin[n] Input Schmitt Trigger Enable Control
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSREN0 : Port A-F Pin[n] High Slew Rate Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSREN1 : Port A-F Pin[n] High Slew Rate Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSREN2 : Port A-F Pin[n] High Slew Rate Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSREN3 : Port A-F Pin[n] High Slew Rate Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSREN4 : Port A-F Pin[n] High Slew Rate Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSREN5 : Port A-F Pin[n] High Slew Rate Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSREN6 : Port A-F Pin[n] High Slew Rate Control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSREN7 : Port A-F Pin[n] High Slew Rate Control
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLEN0 : Port A-F Pull-low Resistor Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLEN1 : Port A-F Pull-low Resistor Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLEN2 : Port A-F Pull-low Resistor Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLEN3 : Port A-F Pull-low Resistor Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLEN4 : Port A-F Pull-low Resistor Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLEN5 : Port A-F Pull-low Resistor Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLEN6 : Port A-F Pull-low Resistor Control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLEN7 : Port A-F Pull-low Resistor Control
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PHEN0 : Port A-F Pull-high Resistor Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PHEN1 : Port A-F Pull-high Resistor Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PHEN2 : Port A-F Pull-high Resistor Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PHEN3 : Port A-F Pull-high Resistor Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PHEN4 : Port A-F Pull-high Resistor Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PHEN5 : Port A-F Pull-high Resistor Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PHEN6 : Port A-F Pull-high Resistor Control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PHEN7 : Port A-F Pull-high Resistor Control
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF0 : Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF1 : Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF2 : Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF3 : Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF4 : Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF5 : Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF6 : Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF7 : Port A-F Pin[n] Digital Function Disable Control Each of these bits is used to control if the digital input/output path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.