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TMR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x80 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

Registers

TIMER0_CTL

TIMER0_CAP

TIMER0_EXTCTL

TIMER0_EINTSTS

TIMER1_CTL

TIMER1_CMP

TIMER1_INTSTS

TIMER1_CNT

TIMER1_CAP

TIMER1_EXTCTL

TIMER1_EINTSTS

TIMER0_CMP

TIMER_CCAPCTL

TIMER_CCAP0

TIMER_CCAP1

TIMER_CCAP2

TIMER_CCAP3

TIMER0_INTSTS

TIMER2_CTL

TIMER2_CMP

TIMER2_INTSTS

TIMER2_CNT

TIMER2_CAP

TIMER2_EXTCTL

TIMER2_EINTSTS

TIMER0_CNT


TIMER0_CTL

Timer0 Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_CTL TIMER0_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC CMPCTL WKEN EXTCNTEN ACTSTS RSTCNT OPMODE INTEN CNTEN ICEDEBUG

PSC : Prescale Counter
bits : 0 - 7 (8 bit)
access : read-write

CMPCTL : TIMERx_CMP Mode Control
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

In One-shot or Periodic mode, when write new CMPDAT, timer counter will reset

#1 : 1

In One-shot or Periodic mode, when write new CMPDAT if new CMPDAT CNT (TIMERx_CNT[23:0])(current counter) , timer counter keep counting and will not reset. If new CMPDAT = CNT(current counter) , timer counter will reset

End of enumeration elements list.

WKEN : Wake-up Enable Control When WKEN is set and the TIF or CAPIF is set, the timer controller will generator a wake-up trigger event to CPU.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Wake-up trigger event Disabled

#1 : 1

Wake-up trigger event Enabled

End of enumeration elements list.

EXTCNTEN : Counter Mode Enable Control This bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 'Event Counting Mode' for detail description.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

External event counter mode Disabled

#1 : 1

External event counter mode Enabled

End of enumeration elements list.

ACTSTS : Timer Active Status (Read Only) This bit indicates the 24-bit up counter status.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

#0 : 0

24-bit up counter is not active

#1 : 1

24-bit up counter is active

End of enumeration elements list.

RSTCNT : Timer Reset
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit if ACTSTS is 1

End of enumeration elements list.

OPMODE : Timer Operating Mode
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

#00 : 0

The timer is operating in One-shot mode. The associated interrupt signal is generated once (if INTEN is enabled) and CNTEN is automatically cleared by hardware

#01 : 1

The timer is operating in Periodic mode. The associated interrupt signal is generated periodically (if INTEN is enabled)

#10 : 2

The timer is operating in Toggle mode. The interrupt signal is generated periodically (if INTEN is enabled). The associated signal (tout) is changing back and forth with 50 percent duty cycle

#11 : 3

The timer is operating in Continuous Counting mode. The associated interrupt signal is generated when TIMERx_CNT = TIMERx_CMP (if INTEN is enabled). However, the 24-bit up-timer counts continuously. Please refer to 6.6.5.6 for detailed description about Continuous Counting mode operation

End of enumeration elements list.

INTEN : Interrupt Enable Control Note: If this bit is enabled, when the timer interrupt flag (TIF) is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer Interrupt function Disabled

#1 : 1

Timer Interrupt function Enabled

End of enumeration elements list.

CNTEN : Timer Enable Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Stops/Suspends counting

#1 : 1

Starts counting

End of enumeration elements list.

ICEDEBUG : ICE Debug Mode Acknowledge Disable Control (Write Protect) Timer counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode acknowledgement effects TIMER counting

#1 : 1

ICE debug mode acknowledgement Disabled

End of enumeration elements list.


TIMER0_CAP

Timer0 Capture Data Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIMER0_CAP TIMER0_CAP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPDAT

CAPDAT : Timer Capture Data Register When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on ACMPOx matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
bits : 0 - 23 (24 bit)
access : read-only


TIMER0_EXTCTL

Timer0 Extended Event Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_EXTCTL TIMER0_EXTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTPHASE CAPEDGE CAPEN CAPFUNCS CAPIEN ECNTDBEN CAPMODE

CNTPHASE : Timer External Count Pin Phase Detect Selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

A falling edge of TMx (x = 0~2) pin will be counted

#1 : 1

A rising edge of TMx (x = 0~2) pin will be counted

End of enumeration elements list.

CAPEDGE : Timer Capture Pin Edge Detection
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 0

A falling edge on ACMP_CO0 will be detected

#01 : 1

A rising edge on ACMP_CO0 will be detected

#10 : 2

Either rising or falling edge on ACMP_CO0 will be detected

#11 : 3

Reserved.

End of enumeration elements list.

CAPEN : Timer Capture Function Enable Control This bit enables the Timer Capture Function
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer Capture Function Disabled

#1 : 1

Timer Capture Function Enabled

End of enumeration elements list.

CAPFUNCS : Capture Function Select Bit Note1: When CAPFUNCS is 0, transition on ACMPOx is using to save the 24-bit timer counter value to CAPDAT register. Note2: When CAPFUNCS is 1, transition on ACMPOx is using to reset the 24-bit timer counter value.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Capture Mode Enabled

#1 : 1

Reset Mode Enabled

End of enumeration elements list.

CAPIEN : Timer Capture Interrupt Enable Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer Capture Interrupt Disabled

#1 : 1

Timer Capture Interrupt Enabled

End of enumeration elements list.

ECNTDBEN : Timer Counter Input Pin De-bounce Enable Control
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

TMx (x = 0~2) pin de-bounce Disabled

#1 : 1

TMx (x = 0~2) pin de-bounce Enabled

End of enumeration elements list.

CAPMODE : Capture Mode Select Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer counter reset function or free-counting mode of timer capture function

#1 : 1

Trigger-counting mode of timer capture function

End of enumeration elements list.


TIMER0_EINTSTS

Timer0 Extended Event Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_EINTSTS TIMER0_EINTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPIF

CAPIF : Timer Capture Interrupt Flag This bit indicates the timer external capture interrupt flag status. Note1: This bit is cleared by writing 1 to it. Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on ACMPOx matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer Capture interrupt did not occur

#1 : 1

Timer Capture interrupt occurred

End of enumeration elements list.


TIMER1_CTL

Timer1 Control and Status Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_CTL TIMER1_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER1_CMP

Timer1 Compare Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_CMP TIMER1_CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER1_INTSTS

Timer1 Interrupt Status Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_INTSTS TIMER1_INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER1_CNT

Timer1 Data Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_CNT TIMER1_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER1_CAP

Timer1 Capture Data Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_CAP TIMER1_CAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER1_EXTCTL

Timer1 Extended Event Control Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_EXTCTL TIMER1_EXTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER1_EINTSTS

Timer1 Extended Event Interrupt Status Register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_EINTSTS TIMER1_EINTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER0_CMP

Timer0 Compare Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_CMP TIMER0_CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPDAT

CMPDAT : Timer Compared Value CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF flag will set to 1. Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. Note2: When Timer is operating at Continuous Counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into CMPDAT field. But if Timer is operating at other modes except Periodic mode on M05xxDN/DE, the 24-bit up counter will restart counting and using newest CMPDAT value to be the timer compared value if software writes a new value into CMPDAT field.
bits : 0 - 23 (24 bit)
access : read-write


TIMER_CCAPCTL

Timer Continuous Capture Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER_CCAPCTL TIMER_CCAPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCAPEN INV CNTSEL CAPCHSEL CNTSEL2 CAPR1F CAPF1F CAPR2F CAPF2F CCAPIEN NFDIS NFCLKS

CCAPEN : Continuous Capture Enable Control This bit is to be enabled the continuous capture function. Note: This bit is cleared by hardware automatically when capture operation finish or writing 0 to it
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled Continuous capture function

#1 : 1

Enabled Continuous capture function

End of enumeration elements list.

INV : Input Signal Inverse Invert the input signal which be captured.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

None

#1 : 1

Inverse

End of enumeration elements list.

CNTSEL : Capture Timer Selection Select the timer to continuous capture the input signal.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

TIMER0

#01 : 1

TIMER1

#10 : 2

SysTick

#11 : 3

See CNTSEL2

End of enumeration elements list.

CAPCHSEL : Capture Timer Channel Selection Select the channel to be the continuous capture event.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

CCAP_P0

#1 : 1

CCAP_P1

End of enumeration elements list.

CNTSEL2 : Capture Timer2 Selection
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

#000 : 0

TIMER2

#001 : 1

Disable

End of enumeration elements list.

CAPR1F : Capture Rising Edge 1 Flag First rising edge already captured, this bit will be set to 1. Note: This bit is cleared by hardware automatically when writing 1 to this bit.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

None

#1 : 1

CAPDAT(TIMER_CCAP0[23:0]) data is ready for read

End of enumeration elements list.

CAPF1F : Capture Falling Edge 1 Flag First falling edge already captured, this bit will be set to 1. Note: This bit is cleared by hardware automatically when writing 1 to this bit.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

None

#1 : 1

CAPDAT(TIMER_CCAP1[23:0]) data is ready for read

End of enumeration elements list.

CAPR2F : Capture Rising Edge 2 Flag Second rising edge already captured, this bit will be set to 1. Note: This bit is cleared by hardware automatically when writing 1 to this bit.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

None

#1 : 1

CAPDAT(TIMER_CCAP2[23:0]) data is ready for read

End of enumeration elements list.

CAPF2F : Capture Falling Edge 2 Flag Second falling edge already captured, this bit will be set to 1 Note: This bit is cleared by hardware automatically when writing 1 to this bit.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

None

#1 : 1

CAPDAT(TIMER_CCAP3[23:0]) data is ready for read

End of enumeration elements list.

CCAPIEN : Capture Interrupt Enable Control
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

Interrupt Disabled

#01 : 1

Capture Rising Edge 1 and Falling Edge 1 interrupt Enabled

#10 : 2

Capture Rising Edge 1, Falling dege1 and Rising Edge 2 interrupt Enabled

#11 : 3

Capture Rising Edge 1, Falling dege1, Rising Edge 2 and Falling Edge 2 interrupt Enabled

End of enumeration elements list.

NFDIS : Disable Input Capture Noise Filter
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Noise filter of Input Capture Enabled

#1 : 1

The noise filter of Input Capture Disabled

End of enumeration elements list.

NFCLKS : Noise Filter Clock Pre-divided Selection To determine the sampling frequency of the Noise Filter clock
bits : 25 - 26 (2 bit)
access : read-write

Enumeration:

#00 : 0

CAPCLK

#01 : 1

CAPCLK / 2

#10 : 2

CAPCLK / 4

#11 : 3

CAPCLK / 16

End of enumeration elements list.


TIMER_CCAP0

Timer Continuous Capture Data Register 0
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIMER_CCAP0 TIMER_CCAP0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPDAT

CAPDAT : Timer Continuous Capture Data Register TIMER_CCAP0 store the timer count value of first rising edge TIMER_CCAP1 store the timer count value of first falling edge TIMER_CCAP2 store the timer count value of second rising edge TIMER_CCAP3 store the timer count value of second falling edge
bits : 0 - 23 (24 bit)
access : read-only


TIMER_CCAP1

Timer Continuous Capture Data Register 1
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER_CCAP1 TIMER_CCAP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER_CCAP2

Timer Continuous Capture Data Register 2
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER_CCAP2 TIMER_CCAP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER_CCAP3

Timer Continuous Capture Data Register 3
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER_CCAP3 TIMER_CCAP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER0_INTSTS

Timer0 Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_INTSTS TIMER0_INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF TWKF

TIF : Timer Interrupt Flag This bit indicates the interrupt flag status of Timer while CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT value. Note: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

CNT value matches the CMPDAT value

End of enumeration elements list.

TWKF : Timer Wake-up Flag This bit indicates the interrupt wake-up flag status of Timer. Note: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer does not cause chip wake-up

#1 : 1

Chip wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated

End of enumeration elements list.


TIMER2_CTL

Timer2 Control and Status Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_CTL TIMER2_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER2_CMP

Timer2 Compare Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_CMP TIMER2_CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER2_INTSTS

Timer2 Interrupt Status Register
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_INTSTS TIMER2_INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER2_CNT

Timer2 Data Register
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_CNT TIMER2_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER2_CAP

Timer2 Capture Data Register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_CAP TIMER2_CAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER2_EXTCTL

Timer2 Extended Event Control Register
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_EXTCTL TIMER2_EXTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER2_EINTSTS

Timer2 Extended Event Interrupt Status Register
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_EINTSTS TIMER2_EINTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER0_CNT

Timer0 Data Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIMER0_CNT TIMER0_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Timer Data Register If CNTEN is set to 1, CNT register value will be updated continuously to monitor 24-bit up counter value.
bits : 0 - 23 (24 bit)
access : read-only



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