ECAP_CNT (CNT)

ECAP_CNTCMP (CNTCMP)

ECAP_CTL0 (CTL0)

ECAP_CTL1 (CTL1)

ECAP_STS (STS)

ECAP_CTL2 (CTL2)

ECAP_HLD0 (HLD0)

ECAP_HLD1 (HLD1)

ECAP_HLD2 (HLD2)

CNT : Input Capture Timer/Counter (24-bit Up Counter) The input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider output which the ECAP_CLK is divided by 1, 4, 16, 32, 64, 96, 112 or 128.
bits : 0 - 23 (24 bit)
access : read-write

CNTCMP : Input Capture Counter Compare Register
bits : 0 - 23 (24 bit)
access : read-write

NFCLKS : Noise Filter Clock Pre-divided Selection To determine the sampling frequency of the Noise Filter clock
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPNFDIS : Disable Input Capture Noise Filter
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC0EN : Enable Port Pin IC0 Input to Input Capture Unit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC1EN : Enable Port Pin IC1 Input to Input Capture Unit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC2EN : Enable Port Pin IC2 Input to Input Capture Unit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAP0SEL : CAP0 Input Source Selection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAP1SEL : CAP1 Input Source Selection
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAP2SEL : CAP2 Input Source Selection
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF0IEN : Enable Input Capture Channel 0 Interrupt
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF1IEN : Enable Input Capture Channel 1 Interrupt
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF2IEN : Enable Input Capture Channel 2 Interrupt
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPOVIEN : Enable CAPOVF Trigger Input Capture Interrupt
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCMPIEN : Enable CAPCMPF Trigger Input Capture Interrupt
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTST : Input Capture Counter Start Bit Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (ECAP_CLK).
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCLR : Input Capture Counter Clear by Compare-match Control
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTCLR : Input Capture Counter Clear by Capture Events Control If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when any one of capture events (CAPTF0~3) occurs.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLDEN : The Reload Function Enable Control Setting this bit to enable reload function. If the reload control is enabled, an overflow event (CAPOVF) or capture events (CAPTFx) will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPEN : The Compare Function Enable Control The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEN : Input Capture Timer/Counter Enable Control
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPPHGEN : Input Capture Flag Trigger PWM Phase Change Function Enable Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEDG0 : Channel 0 Captured Edge Selection Input capture can detect falling edge change only, rising edge change only or one of both edge change
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEDG1 : Channel 1 Captured Edge Selection Input capture can detect falling edge change only, rising edge change only or one of both edge change
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEDG2 : Channel 2 Captured Edge Selection Input capture can detect falling edge change only, rising edge change only or one of both edge change
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPRLDS : ECAP_CNT Reload Trigger Source Selection
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPDIV : Capture Timer Clock Divide Selection The capture timer clock has a pre-divider with eight divided options controlled by CAPDIV[2:0].
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTSRC : Capture Timer/Counter Clock Source Selection Select the capture timer/counter clock source
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF0 : Input Capture Channel 0 Captured Flag When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. Note: This bit is only cleared by writing 1 to itself through software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF1 : Input Capture Channel 1 Captured Flag When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. Note: This bit is only cleared by writing 1 to itself through software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF2 : Input Capture Channel 2 Captured Flag When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. Note: This bit is only cleared by writing 1 to itself through software.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCMPF : Input Capture Compare-match Flag If the input capture compare function is enabled, the flag is set by hardware while capture counter (CNT) up counts and reach to the CNTCMP value. Note: This bit is only cleared by writing 1 to itself through software.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPOVF : Input Capture Counter Overflow Flag Flag is set by hardware when input capture up counter (CNT) overflows from 0x00FF_FFFF to 0. Note: This bit is only cleared by writing 1 to itself through software.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ECAP0 : Input Capture Source 0 Status (Read Only) Input capture Source 0 (ECAP_P0) status. It is read only. (The bit is read only and write is ignored)
bits : 8 - 8 (1 bit)
access : read-only

ECAP1 : Input Capture Source 1 Status (Read Only) Input capture Source 1 (ECAP_P1) status. It is read only. (The bit is read only and write is ignored)
bits : 9 - 9 (1 bit)
access : read-only

ECAP2 : Input Capture Source 2 Status (Read Only) Input captureSource 2 (ECAP_P2) status. It is read only. (The bit is read only and write is ignored)
bits : 10 - 10 (1 bit)
access : read-only

RLDS0EN : CATF0 Event Trigger Enable for RLD Event Source
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLDS1EN : CAPTF1 Event Trigger Enable for RLD Event Source
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLDS2EN : CAPTF2 Event Trigger Enable for RLD Event Source
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLDOVSEN : CAPOVF Event Trigger Enable for RLD Event Source
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLDMS : RLD Function Trigger Event Source Mode Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLRS0EN : CAPTF0 Event Trigger Enable for CPTCLR Event Source
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLRS1EN : CAPTF1 Event Trigger Enable for CPTCLR Event Source
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLRS2EN : CAPTF2 Event Trigger Enable for CPTCLR Event Source
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTCLRMS : CPTCLR Function Trigger Event Source Mode Selection
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HOLD : Input Capture Counter Hold Register When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register. Each input channel has itself holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
bits : 0 - 23 (24 bit)
access : read-write