\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x24 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x54 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x78 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
EPWM Negative Polarity Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NEGPOLAR0 : PWM0 Negative Polarity Control
The register bit controls polarity/active state of real PWM output.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output is active high
#1 : 1
PWM output is active low
End of enumeration elements list.
NEGPOLAR1 : PWM1 Negative Polarity Control
The register bit controls polarity/active state of real PWM output.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output is active high
#1 : 1
PWM output is active low
End of enumeration elements list.
NEGPOLAR2 : PWM2 Negative Polarity Control
The register bit controls polarity/active state of real PWM output.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output is active high
#1 : 1
PWM output is active low
End of enumeration elements list.
NEGPOLAR3 : PWM3 Negative Polarity Control
The register bit controls polarity/active state of real PWM output.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output is active high
#1 : 1
PWM output is active low
End of enumeration elements list.
NEGPOLAR4 : PWM4 Negative Polarity Control
The register bit controls polarity/active state of real PWM output.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output is active high
#1 : 1
PWM output is active low
End of enumeration elements list.
NEGPOLAR5 : PWM5 Negative Polarity Control
The register bit controls polarity/active state of real PWM output.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output is active high
#1 : 1
PWM output is active low
End of enumeration elements list.
EPWM Comparator Register 0
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : PWM Comparator Register
CMP determines the PWM Duty.
Edge-aligned mode: where xy, could be 01, 23, 45 depending on the selected PWM channel.
Note: Any write to CMPn will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write
CMPU : PWM Comparator Register for UP Counter in Center-aligned Asymmetric Mode
CMPU PERIOD: @ up counter PWM output is keep to Max. duty.
bits : 16 - 31 (16 bit)
access : read-write
EPWM Comparator Register 1
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Comparator Register 2
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Comparator Register 3
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Comparator Register 4
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Comparator Register 5
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Data Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : PWM Data Register
User can monitor CNT to know the current value in 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only
CNTDIR : PWM Counter (Up/Down) Direction
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM counter is down counting
#1 : 1
PWM counter is up counting
End of enumeration elements list.
EPWM Clock Select Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : EPWM Clock Divider (9 Step Divider)
Select clock input for PWM timer
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
1 (HCLK / 2^0)
#0001 : 1
1/2 (HCLK / 2^1)
#0010 : 2
1/4 (HCLK / 2^2)
#0011 : 3
1/8 (HCLK / 2^3)
#0100 : 4
1/16 (HCLK / 2^4)
#0101 : 5
1/32 (HCLK / 2^5)
#0110 : 6
1/64 (HCLK / 2^6)
#0111 : 7
1/128 (HCLK / 2^7)
#1000 : 8
1/256 (HCLK / 2^8)
End of enumeration elements list.
EPWM Interrupt Enable Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIEN : PWM Channel 0 Period Interrupt Enable Control
for Edge-aligned and Center-aligned
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Period interruptDisabled
#1 : 1
EPWM Period interruptEnabled
End of enumeration elements list.
CMPUIEN0 : PWM Channel 0 UP Interrupt Enable Control
UP for Center-aligned only
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_CH0 PWM UP counter reaches EPWM_CMPDAT0 interruptDisabled
#1 : 1
EPWM_CH0 PWM UP counter reaches EPWM_CMPDAT0 interruptEnabled
End of enumeration elements list.
CMPUIEN1 : PWM Channel 1 UP Interrupt Enable Control
UP for Center-aligned only
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_CH1 PWM UP counter reaches EPWM_CMPDAT1 interruptDisabled
#1 : 1
EPWM_CH1 PWM UP counter reaches EPWM_CMPDAT1 interruptEnabled
End of enumeration elements list.
CMPUIEN2 : PWM Channel 2 UP Interrupt Enable Control
UP for Center-aligned only
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_CH2 PWM UP counter reaches EPWM_CMPDAT2 interruptDisabled
#1 : 1
EPWM_CH2 PWM UP counter reaches EPWM_CMPDAT2 interruptEnabled
End of enumeration elements list.
CMPUIEN3 : PWM Channel 3 UP Interrupt Enable Control
UP for Center-aligned only
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_CH3 PWM UP counter reaches EPWM_CMPDAT3 interruptDisabled
#1 : 1
EPWM_CH3 PWM UP counter reaches EPWM_CMPDAT3 interruptEnabled
End of enumeration elements list.
CMPUIEN4 : PWM Channel 4 UP Interrupt Enable Control
UP for Center-aligned only
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_CH4 PWM UP counter reaches EPWM_CMPDAT4 interrupt Disabled
#1 : 1
EPWM_CH4 PWM UP counter reaches EPWM_CMPDAT4 interrupt Enabled
End of enumeration elements list.
CMPUIEN5 : PWM Channel 5 UP Interrupt Enable Control
UP for Center-aligned only
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel 5 UP Interrupt Disabled
#1 : 1
Interruptwhen EPWM_CH5 PWM UP counter reaches EPWM_CMPDAT5 Enabled
End of enumeration elements list.
BRK0IEN : Fault Brake0 Interrupt Enable Control
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
BRK0IF trigger PWM interrupt Disabled
#1 : 1
BRK0IF trigger PWM interrupt Enabled
End of enumeration elements list.
BRK1IEN : Fault Brake1 Interrupt Enable Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
BRK1IF trigger PWM interrupt Disabed
#1 : 1
BRK1IF trigger PWM interrupt Enabled
End of enumeration elements list.
CIEN : PWM Central Interrupt Enable Control
for Center-aligned only
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interruptwhen EPWM Central Enabled
#1 : 1
Interruptwhen EPWM Central Enabled
End of enumeration elements list.
CMPDIEN0 : PWM Channel 0 DOWN Interrupt Enable Control
DOWN for Edge-aligned and Center-aligned
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interruptcompare Disabled
#1 : 1
interruptwhen EPWM_CH0 PWM DOWN counter reaches EPWM_CMPDAT0 Enabled
End of enumeration elements list.
CMPDIEN1 : PWM Channel 1 DOWN Interrupt Enable Control
DOWN for Edge-aligned and Center-aligned
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interruptcompare Disabled
#1 : 1
interruptwhen EPWM_CH1 PWM DOWN counter reaches EPWM_CMPDAT1 Enabled
End of enumeration elements list.
CMPDIEN2 : PWM Channel 2 DOWN Interrupt Enable Control
DOWN for Edge-aligned and Center-aligned
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interruptcompare Disabled
#1 : 1
interruptwhen EPWM_CH2 PWM DOWN counter reaches EPWM_CMPDAT2 Enabled
End of enumeration elements list.
CMPDIEN3 : PWM Channel 3 DOWN Interrupt Enable Control
DOWN for Edge-aligned and Center-aligned
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interruptcompare Disabled
#1 : 1
interruptwhen EPWM_CH3 PWM DOWN counter reaches EPWM_CMPDAT3 Enabled
End of enumeration elements list.
CMPDIEN4 : PWM Channel 4 DOWN Interrupt Enable Control
DOWN for Edge-aligned and Center-aligned
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interruptcompare Disabled
#1 : 1
interruptwhen EPWM_CH4 PWM DOWN counter reaches EPWM_CMPDAT4 Enabled
End of enumeration elements list.
CMPDIEN5 : PWM Channel 5 DOWN Interrupt Enable Control
DOWN for Edge-aligned and Center-aligned
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interruptcompare Disabled
#1 : 1
Interruptwhen EPWM_CH5 PWM DOWN counter reaches EPWM_CMPDAT5 Enabled
End of enumeration elements list.
EPWM Interrupt Status Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIF : PWM Channel 0 Period Interrupt Flag
Edge-aligned mode:
Flag is set by hardware when PWM down counter reaches zero point.
Center-aligned mode:
Flag is set by hardware when PWM down counter reaches zero point and then up counter reaches EPWM_PERIOD.
Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
CMPUIF0 : PWM Channel 0 UP Interrupt Flag
Flag is set by hardware when a channel 0 PWM UP counter reaches PWM_CMPDAT0. Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write
CMPUIF1 : PWM Channel 1 UP Interrupt Flag
Flag is set by hardware when a channel 1 PWM UP counter reaches PWM_CMPDAT1. Software can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write
CMPUIF2 : PWM Channel 2 UP Interrupt Flag
Flag is set by hardware when a channel 2 PWM UP counter reaches PWM_CMPDAT2. Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write
CMPUIF3 : PWM Channel 3 UP Interrupt Flag
Flag is set by hardware when a channel 3 PWMUP counter reaches PWM_CMPDAT3. Software can write 1 to clear this bit.
bits : 11 - 11 (1 bit)
access : read-write
CMPUIF4 : PWM Channel 4 UP Interrupt Flag
Flag is set by hardware when a channel 4 PWM UP counter reaches PWM_CMPDAT4. Software can write 1 to clear this bit.
bits : 12 - 12 (1 bit)
access : read-write
CMPUIF5 : PWM Channel 5 UP Interrupt Flag
Flag is set by hardware when a channel 5 PWM UP counter reaches PWM_CMPDAT5. Software can write 1 to clear this bit.
bits : 13 - 13 (1 bit)
access : read-write
BRK0IF : PWM Brake0 Flag
Note: Software can write 1 to clear this bit.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Brake does not recognize a falling signal at BKP0
#1 : 1
When PWM Brake detects a falling signal at pin BKP0, this flag will be set to high
End of enumeration elements list.
BRK1IF : PWM Brake1 Flag
Note: Software can write 1 to clear this bit.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Brake does not recognize a falling signal at BKP1
#1 : 1
When PWM Brake detects a falling signal at pin BKP1, this flag will be set to high
End of enumeration elements list.
CIF : PWM Channel 0 Central Interrupt Flag
Flag is set by hardware when PWM down counter reaches zero point. Software can write 1 to clear this bit.
bits : 18 - 18 (1 bit)
access : read-write
BRK0LOCK : PWM Brake0 Locked
Note: Software can write 1 to clear this bit.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Brake does not recognize a falling signal at BKP0
#1 : 1
When PWM Brake detects a falling signal at pin BKP0, this flag will be set to high, when this bit set high, it helps breaking PWM output even interrupt flag BRK0IF was cleared by CPU before jumping out from sub-routine
End of enumeration elements list.
BRKP0IF : BRK Pin0 Status Flag
Flag is set by pin PWM_BRK_P0 with low pulse event. Software can write 1 to clear this bit.
bits : 20 - 20 (1 bit)
access : read-write
BRKP1IF : BRK Pin1 Status Flag
Flag is set by pin PWM_BRK_P1 with low pulse event. Software can write 1 to clear this bit.
bits : 21 - 21 (1 bit)
access : read-write
BRKP2IF : BRK Pin2 Status Flag
Flag is set by pin PWM_BRK_P2 with low pulse event. Software can write 1 to clear this bit.
bits : 22 - 22 (1 bit)
access : read-write
CMPDIF0 : PWM Channel 0 DOWN Interrupt Flag
Flag is set by hardware when a channel 0 PWM DOWN counter reaches EPWM_CMPDAT0. Software can write 1 to clear this bit.
bits : 24 - 24 (1 bit)
access : read-write
CMPDIF1 : PWM Channel 1 DOWN Interrupt Flag
Flag is set by hardware when a channel 1 PWM DOWN counter reaches EPWM_CMPDAT1. Software can write 1 to clear this bit.
bits : 25 - 25 (1 bit)
access : read-write
CMPDIF2 : PWM Channel 2 DOWN Interrupt Flag
Flag is set by hardware when a channel 2 PWM DOWN counter reaches EPWM_CMPDAT2. Software can write 1 to clear this bit.
bits : 26 - 26 (1 bit)
access : read-write
CMPDIF3 : PWM Channel 3 DOWN Interrupt Flag
Flag is set by hardware when a channel 3 PWM DOWN counter reaches EPWM_CMPDAT3. Software can write 1 to clear this bit.
bits : 27 - 27 (1 bit)
access : read-write
CMPDIF4 : PWM Channel 4 DOWN Interrupt Flag
Flag is set by hardware when a channel 4 PWM DOWN counter reaches EPWM_CMPDAT4. Software can write 1 to clear this bit.
bits : 28 - 28 (1 bit)
access : read-write
CMPDIF5 : PWM Channel 5 DOWN Interrupt Flag
Flag is set by hardware when a channel 5 PWM DOWN counter reaches EPWM_CMPDAT5. Software can write 1 to clear this bit.
bits : 29 - 29 (1 bit)
access : read-write
EPWM BRK Low Voltage Detect Resume Delay
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELAY : PWM BRK Low Voltage Detect Resume Delay
12 bits Down-Counter
bits : 0 - 11 (12 bit)
access : read-write
EPWM Fault Brake Control Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK0EN : Brake0 Function Enable Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake0 detect function Disabled
#1 : 1
Brake0 detect function Enabled
End of enumeration elements list.
BRK1EN : Brake1 Function Enable Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake1 detect function Disabled
#1 : 1
Brake1 detect function Enabled
End of enumeration elements list.
BRK0A0EN : BRK0 Source From ACMP0 Enable Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
BRK0 Source From ACMP0 Disabled
#1 : 1
BRK0 Source From ACMP0 Enabled
End of enumeration elements list.
BK0ADCEN : BRK0 Source From ADC Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
BRK0 Source From ADC Disabled
#1 : 1
BRK0 Source From ADC Enabled
End of enumeration elements list.
BRK0PEN : BRK0 Source From External Pin Enable Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
BRK0 Source From External Pin Disabled
#1 : 1
BRK0 Source From External Pin Enabled
End of enumeration elements list.
BRKPIN0EN : BRK Source From External Pin 0 Enable Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
BRK Source From External PWM_BRK_P0 Disabled
#1 : 1
BRK Source From External PWM_BRK_P0 Enabled
End of enumeration elements list.
BRKPIN1EN : BRK Source From External Pin 1 Enable Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
BRK Source From External PWM_BRK_P1 Disabled
#1 : 1
BRK Source From External PWM_BRK_P1 Enabled
End of enumeration elements list.
BRKPIN2EN : BRK Source From External Pin 2 Enable Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
BRK Source From External PWM_BRK_P2 Disabled
#1 : 1
BRK Source From External PWM_BRK_P2 Enabled
End of enumeration elements list.
SWBRK : Software Break
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software break and back to normal PWM function Disabled
#1 : 1
Issue Software break Enabled
End of enumeration elements list.
BRK1A0EN : BRK1 Source From ACMP0 Enable Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
BRK1 Source From ACMP0 Disabled
#1 : 1
BRK1 Source From ACMP0 Enabled
End of enumeration elements list.
BK1ADCEN : BRK1 Source From ADC Enable Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
BRK1 Source From ADC Disabled
#1 : 1
BRK1 Source From ADC Enabled
End of enumeration elements list.
BRK1PEN : BRK1 Source From External Pin Enable Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
BRK1 Source From External Pin Disabled
#1 : 1
BRK1 Source From External Pin Enabled
End of enumeration elements list.
LVDBKEN : Low-level Detection Trigger PWM Brake Function 1 Enable Control
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function 1 triggered by Low-level detection Disabled
#1 : 1
Brake Function 1 triggered by Low-level detection Enabled
End of enumeration elements list.
LVDTYPE : Low-level Detection Resume Type
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake resume at BRK resume delay counter counting to 0
#1 : 1
Brake resume at period edge
End of enumeration elements list.
NFCLKSEL : Noise Filter Clock Pre-divide Selection
To determine the sampling frequency of the Noise Filter clock.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
EPWM_CLK
#001 : 1
EPWM _CLK/2
#010 : 2
EPWM _CLK/4
#011 : 3
EPWM _CLK/8
#100 : 4
EPWM _CLK/16
#101 : 5
EPWM _CLK/32
#110 : 6
EPWM _CLK/64
#111 : 7
EPWM _CLK/128
End of enumeration elements list.
BKOD0 : PWM Channel 0 Brake Output Selection
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output low when fault brake conditions asserted
#1 : 1
PWM output high when fault brake conditions asserted
End of enumeration elements list.
BKOD1 : PWM Channel 1 Brake Output Selection
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output low when fault brake conditions asserted
#1 : 1
PWM output high when fault brake conditions asserted
End of enumeration elements list.
BKOD2 : PWM Channel 2 Brake Output Selection
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output low when fault brake conditions asserted
#1 : 1
PWM output high when fault brake conditions asserted
End of enumeration elements list.
BKOD3 : PWM Channel 3 Brake Output Selection
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output low when fault brake conditions asserted
#1 : 1
PWM output high when fault brake conditions asserted
End of enumeration elements list.
BKOD4 : PWM Channel 4 Brake Output Selection
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output low when fault brake conditions asserted
#1 : 1
PWM output high when fault brake conditions asserted
End of enumeration elements list.
BKOD5 : PWM Channel 5 Brake Output Selection
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output low when fault brake conditions asserted
#1 : 1
PWM output high when fault brake conditions asserted
End of enumeration elements list.
NFPEN : Noise Filter for External Brake Input Pin (BRAKE) Enable Control
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise Filter for External Brake Input Pin (BRAKE) Disabled
#1 : 1
Noise Filter for External Brake Input Pin (BRAKE) Enabled
End of enumeration elements list.
EPWM Dead-zone Interval Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT01 : Dead-zone Interval Register for Pair of Channel0 and Channel1 (PWM0 and PWM1 Pair)
These 8 bits determine dead-zone length.
The unit time of dead-zone length is received from corresponding EPWM_CLKDIV bits.
bits : 0 - 7 (8 bit)
access : read-write
DTCNT23 : Dead-zone Interval Register for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair)
These 8 bits determine dead-zone length.
The unit time of dead-zone length is received from corresponding EPWM_CLKDIV bits.
bits : 8 - 15 (8 bit)
access : read-write
DTCNT45 : Dead-zone Interval Register for Pair of Channel4 and Channel5 (PWM4 and PWM5 Pair)
These 8 bits determine dead-zone length.
The unit time of dead-zone length is received from corresponding EPWM_CLKDIV bits.
bits : 16 - 23 (8 bit)
access : read-write
EPWM Phase Changed Register
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKDAT0 : Enable PWM0 Mask Data
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 state is masked with zero
#1 : 1
PWM0 state is masked with one
End of enumeration elements list.
MSKDAT1 : Enable PWM1 Mask Data
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1 state is masked with zero
#1 : 1
PWM1 state is masked with one
End of enumeration elements list.
MSKDAT2 : Enable PWM2 Mask Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM2 state is masked with zero
#1 : 1
PWM2 state is masked with one
End of enumeration elements list.
MSKDAT3 : Enable PWM3 Mask Data
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM3 state is masked with zero
#1 : 1
PWM3 state is masked with one
End of enumeration elements list.
MSKDAT4 : Enable PWM4 Mask Data
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM4 state is masked with zero
#1 : 1
PWM4 state is masked with one
End of enumeration elements list.
MSKDAT5 : Enable PWM5 Mask Data
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM5 state is masked with zero
#1 : 1
PWM5 state is masked with one
End of enumeration elements list.
BMSKDAT0 : Enable BPWM0 Mask Data
Note: This bit effects BPWM0 only when BPWM_CTL.BP0SYNEPWM is set
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0 state is masked with zero
#1 : 1
BPWM0 state is masked with one
End of enumeration elements list.
BMSKDAT1 : Enable BPWM1 Mask Data
Note: This bit effects BPWM1 only when BPWM_CTL.BP1SYNEPWM is set
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM1 state is masked with zero
#1 : 1
BPWM1 state is masked with one
End of enumeration elements list.
MSKEN0 : Enable PWM0 Mask Function
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 Mask Function Disabled
#1 : 1
PWM0 Mask Function Enabled
End of enumeration elements list.
MSKEN1 : Enable PWM1 Mask Function
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1 Mask Function Disabled
#1 : 1
PWM1 Mask Function Enabled
End of enumeration elements list.
MSKEN2 : Enable PWM2 Mask Function
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM2 Mask Function Disabled
#1 : 1
PWM2 Mask Function Enabled
End of enumeration elements list.
MSKEN3 : Enable PWM3 Mask Function
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM3 Mask Function Disabled
#1 : 1
PWM3 Mask Function Enabled
End of enumeration elements list.
MSKEN4 : Enable PWM4 Mask Function
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM4 Mask Function Disabled
#1 : 1
PWM4 Mask Function Enabled
End of enumeration elements list.
MSKEN5 : Enable PWM5 Mask Function
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM5 Mask Function Disabled
#1 : 1
PWM5 Mask Function Enabled
End of enumeration elements list.
BMSKEN0 : Enable BPWM0 Mask Function
Note: This bit effects BPWM0 only when BPWM_CTL.BP0SYNEPWM is set
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0 Mask Function Disabled
#1 : 1
BPWM0 Mask Function Enabled
End of enumeration elements list.
BMSKEN1 : Enable BPWM1 Mask Function
Note: This bit effects BPWM1 only when BPWM_CTL.BP1SYNEPWM is set
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM1 Mask Function Disabled
#1 : 1
BPWM1 Mask Function Enabled
End of enumeration elements list.
TRGSEL : Phase Change Trigger Selection
Select the trigger condition to load PHCHG from PHCHG_NXT.
When the trigger condition occurs it will load EPWM_PHCHG with PHCHG_NXT.
Phase Change: PWM outputs are masked according with the definition of MSKENn and MSKDATn in EPWM_PHCHG.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Triggered by TMR0_MATCH event
#001 : 1
Triggered by TMR1_MATCH event
#010 : 2
Triggered by CAPPHG_TRG from ECAP. (CAPTF0 | CAPTF1 | CAPTF2)
#011 : 3
Triggered by HALLSTS (EPWM_PHCHGNXT[18:16]) matched (CAP2, CAP1, CAP0) in ECAP..
#100 : 4
Triggered by ACMP0_PBRK event
#101 : 5
Reserved.
#110 : 6
Triggered by TMR2_MATCH event.
#111 : 7
Auto Phase Change Function Disabled
End of enumeration elements list.
A0POSSEL : Alternative Comparator 0 Positive Input Selection
Select the positive input source of ACMP0.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Select ACMP0_P0 (PB.0) as the input of ACMP0
#01 : 1
Select ACMP0_P1 (PB.1) as the input of ACMP0
#10 : 2
Select ACMP0_P2 (PB.2) as the input of ACMP0
#11 : 3
Select ACMP0_P3 (PC.1) as the input of ACMP0
End of enumeration elements list.
ACMP0TEN : ACMP0 Trigger Function Enable Control
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP0 trigger PWM function Disabled
#1 : 1
ACMP0 trigger PWM function Enabled
End of enumeration elements list.
EPWM Next Phase Change Register
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKDAT0 : Enable PWM0 Mask Data Preset Bit
This bit will be load to bit MSKDAT0 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 0 - 0 (1 bit)
access : read-write
MSKDAT1 : Enable PWM1 Mask Data Preset Bit
This bit will be load to bit MSKDAT1 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 1 - 1 (1 bit)
access : read-write
MSKDAT2 : Enable PWM2 Mask Data Preset Bit
This bit will be load to bit MSKDAT2 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 2 - 2 (1 bit)
access : read-write
MSKDAT3 : Enable PWM3 Mask Data Preset Bit
This bit will be load to bit MSKDAT3 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 3 - 3 (1 bit)
access : read-write
MSKDAT4 : Enable PWM4 Mask Data Preset Bit
This bit will be load to bit MSKDAT4 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 4 - 4 (1 bit)
access : read-write
MSKDAT5 : Enable PWM5 Mask Data Preset Bit
This bit will be load to bit MSKDAT5 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 5 - 5 (1 bit)
access : read-write
BMSKDAT0 : Enable BPWM0 Mask Data Preset Bit
This bit will be load to bit BMSKDAT0 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
Note: This bit effects BPWM0 only when BPWM_CTL.BP0SYNEPWM is set
bits : 6 - 6 (1 bit)
access : read-write
BMSKDAT1 : Enable BPWM1 Mask Data Preset Bit
This bit will be load to bit BMSKDAT1 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
Note: This bit effects BPWM1 only when BPWM_CTL.BP1SYNEPWM is set
bits : 7 - 7 (1 bit)
access : read-write
MSKEN0 : Enable PWM0 Mask Function Preset Bit
This bit will be load to bit MSKEN0 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 8 - 8 (1 bit)
access : read-write
MSKEN1 : Enable PWM1 Mask Function Preset Bit
This bit will be load to bit MSKEN1 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 9 - 9 (1 bit)
access : read-write
MSKEN2 : Enable PWM2 Mask Function Preset Bit
This bit will be load to bit MSKEN2 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 10 - 10 (1 bit)
access : read-write
MSKEN3 : Enable PWM3 Mask Function Preset Bit
This bit will be load to bit MSKEN3 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 11 - 11 (1 bit)
access : read-write
MSKEN4 : Enable PWM4 Mask Function Preset Bit
This bit will be load to bit MSKEN4 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 12 - 12 (1 bit)
access : read-write
MSKEN5 : Enable PWM5 Mask Function Preset Bit
This bit will be load to bit MSKEN5 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 13 - 13 (1 bit)
access : read-write
BMSKEN0 : Enable BPWM0 Mask Function Preset Bit
This bit will be load to bit MSKEN4 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
Note: This bit effects BPWM0 only when BPWM_CTL.BP0SYNEPWM is set
bits : 14 - 14 (1 bit)
access : read-write
BMSKEN1 : Enable BPWM1 Mask Function Preset Bit
This bit will be load to bit MSKEN5 in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
Note: This bit effects BPWM1 only when BPWM_CTL.BP1SYNEPWM is set
bits : 15 - 15 (1 bit)
access : read-write
HALLSTS : Predicted Next HALL State
This bit field indicates the predicted hall state at next commutation.
the hardware will compare bits (CAP2, CAP1, CAP0) in timer 2 with HALLSTS [2:0] when any hall state change occurs.
If the comparison is matched it will trigger phase change function.
bits : 16 - 18 (3 bit)
access : read-write
TRGSEL : Phase Change Trigger Selection Preset Bits
This bit field will be load to bit field TRGSEL in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Triggered by TMR0_MATCH event
#001 : 1
Triggered by TMR1_MATCH event
#010 : 2
Triggered by CAPPHG_TRG from ECAP. (CAPTF0 | CAPTF1 | CAPTF2)
#011 : 3
Triggered by HALLSTS (EPWM_PHCHGNXT[18:16]) matched (CAP2, CAP1, CAP0) in ECAP..
#100 : 4
Triggered by ACMP0_PBRK event
#101 : 5
Reserved.
#110 : 6
Triggered by TMR2_MATCH event.
#111 : 7
Auto Phase Change Function Disabled
End of enumeration elements list.
A0POSSEL : Alternative Comparator 0 Positive Input Selection Preset Bits
This bit field will be load to bit field A0POSSEL in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 24 - 25 (2 bit)
access : read-write
ACMP0TEN : ACMP0 Trigger Function Control Preset Bit
This bit will be load to bit ACMP0TEN in EPWM_PHCHG when load trigger condition occurs.
Refer to register EPWM_PHCHG for detailed definition.
bits : 28 - 28 (1 bit)
access : read-write
EPWM Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN0 : PWM- Generator 0 Enable/Disable Start Run
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-timer running Stopped
#1 : 1
Corresponding PWM-timer start run Enabled
End of enumeration elements list.
CNTEN1 : PWM- Generator 1 Enable/Disable Start Run
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-timer running Stopped
#1 : 1
Corresponding PWM-timer start run Enabled
End of enumeration elements list.
CNTEN2 : PWM- Generator 2 Enable/Disable Start Run
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-timer running Stopped
#1 : 1
Corresponding PWM-timer start run Enabled
End of enumeration elements list.
CNTEN3 : PWM- Generator 3 Enable/Disable Start Run
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-timer running Stopped
#1 : 1
Corresponding PWM-timer start run Enabled
End of enumeration elements list.
CNTEN4 : PWM- Generator 4 Enable/Disable Start Run
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-timer running Stopped
#1 : 1
Corresponding PWM-timer start run Enabled
End of enumeration elements list.
CNTEN5 : PWM-generator 5 Enable/Disable Start Run
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-timer running Stopped
#1 : 1
Corresponding PWM-timer start run Enabled
End of enumeration elements list.
CNTMODE : PWM-timer Auto-reload/One-shot Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-shot mode
#1 : 1
Auto-reload mode
End of enumeration elements list.
HCUPDT : Half Cycle Update Enable for Center-aligned Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Update PERIOD CMP at pwm_counter = PERIOD (Period)
#01 : 1
Update PERIOD CMP at pwm_counter = 0
#10 : 2
Update PERIOD CMP at half cycle (counter = 0 PERIOD, both update)
#11 : 3
Update PERIOD CMP at pwm_counter = PERIOD (Period)
End of enumeration elements list.
ASYMEN : Asymmetric Mode in Center-aligned Type
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Symmetric mode in center-aligned type
#1 : 1
Asymmetric mode in center-aligned type
End of enumeration elements list.
DTCNT01 : Dead-zone 0 Generator Enable/Disable (PWM0 and PWM1 Pair for PWM Group)
Note: When the dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-zone 0 Generator Disabled
#1 : 1
Dead-zone 0 Generator Enabled
End of enumeration elements list.
DTCNT23 : Dead-zone 2 Generator Enable/Disable (PWM2 and PWM3 Pair for PWM Group)
Note: When the dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-zone 2 Generator Disabled
#1 : 1
Dead-zone 2 Generator Enabled
End of enumeration elements list.
DTCNT45 : Dead-zone 4 Generator Enable/Disable (PWM4 and PWM5 Pair for PWM Group)
Note: When the dead-zone generator is enabled, the pair of PWM4 and PWM5 becomes a complementary pair for PWM group.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-zone 4 Generator Disabled
#1 : 1
Dead-zone 4 Generator Enabled
End of enumeration elements list.
CNTCLR : Clear PWM Counter Control Bit
Note: It is automatically cleared by hardware.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not clear PWM counter
#1 : 1
16-bit PWM counter cleared to 0x000
End of enumeration elements list.
MODE : PWM Operating Mode Selection
Note: If th complementary mode is selected, the deadtime insertion is active automatically.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Independent mode
#01 : 1
Complementary mode
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
GROUPEN : Group Bit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The signals timing of PWM0, PWM2 and PWM4 are independent
#1 : 1
Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0
End of enumeration elements list.
CNTTYPE : PWM Aligned Type Selection
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-aligned type
#1 : 1
Center-aligned type
End of enumeration elements list.
EPWM Phase Change Alternative Control Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSCTL0 : Positive Input Control for ACMP0
Note: Register ACMP_CTL0 is describe in Comparator Controller chapter
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The input of ACMP0 is controlled by ACMP_CTL0
#1 : 1
The input of ACMP0 is controlled by A0POSSEL in EPWM_PHCHG register
End of enumeration elements list.
EPWM Period Interrupt Accumulation Control Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFAEN : Enable Period Interrupt Accumulation Function
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period Interrupt Accumulation Disabled
#1 : 1
Period Interrupt Accumulation Enabled
End of enumeration elements list.
IFCNT : Period Interrupt Accumulation Counter Value Setting Register (Write Only)
16 step Down-Counter value setting register.
When IFAEN is set, IFCNT value will load into IFDAT and decrase gradually.
bits : 4 - 7 (4 bit)
access : write-only
IFDAT : Period Interrupt Down-counter Data Register (Read Only)
When IFAEN is set, IFDAT will decrease when every PWM Interrupt flag is set,
and when IFDAT reaches 0, the PWM interrupt will occurred and IFCNT will reload to IFDAT.
bits : 12 - 15 (4 bit)
access : read-only
EPWM Period Counter Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : PWM Counter/Timer Loaded Value
PERIODn determines the PWM Period.
Edge-aligned mode: where xy, could be 01, 23, 45 depending on the selected PWM channel.
Note: Any write to PERIODn will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write
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