\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
Basic PWM Pre-scalar Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKPSC01 : Clock Prescaler
Clock input is divided by (CLKPSC01 + 1) before it is fed to the corresponding PWM-timer
bits : 0 - 7 (8 bit)
access : read-write
DTI01 : Dead-zone Interval for Pair of Channel 0 and Channel 1
These 8-bit determine the Dead-zone length.
bits : 16 - 23 (8 bit)
access : read-write
Basic PWM Comparator Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : PWM Comparator Register
CMP determines the PWM duty.
Note: Any write to PERIOD will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write
Basic PWM Data Register 0
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : PWM Data Register
User can monitor CNT to know the current value in 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-only
Basic PWM Period Counter Register 1
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Basic PWM Comparator Register 1
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Basic PWM Data Register 1
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Basic PWM Clock Source Divider Select Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV0 : PWM Timer 0 Clock Source Divider Selection
Select clock source divider for PWM timer 0.
(Table is the same as CLKDIV1)
bits : 0 - 2 (3 bit)
access : read-write
CLKDIV1 : PWM Timer 1 Clock Source Divider Selection
Select clock source divider for PWM timer 1.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
1/2
#001 : 1
1/4
#010 : 2
1/8
#011 : 3
1/16
#100 : 4
1
End of enumeration elements list.
Basic PWM Interrupt Enable Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIEN0 : BPWM Channel 0 Period Interrupt Enable Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel 0 Period Interrupt Disabled
#1 : 1
BPWM Channel 0 Period Interrupt Enabled
End of enumeration elements list.
PIEN1 : BPWM Channel 1 Period Interrupt Enable Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel 1 Period Interrupt Disabled
#1 : 1
BPWM Channel 1 Period Interrupt Enabled
End of enumeration elements list.
DIEN0 : BPWM Channel 0 Duty Interrupt Enable Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel 0 Duty Interrupt Disabled
#1 : 1
BPWM Channel 0 Duty Interrupt Enabled
End of enumeration elements list.
DIEN1 : BPWM Channel 1 Duty Interrupt Enable Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel 1 Duty Interrupt Disabled
#1 : 1
BPWM Channel 1 Duty Interrupt Enabled
End of enumeration elements list.
PINTTYPE : BPWM Interrupt Period Type Selection
Note: This bit is effective when BPWM in Center-aligned type only.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIFn will be set if BPWM counter underflow
#1 : 1
PIFn will be set if BPWM counter matches PERIODn register
End of enumeration elements list.
Basic PWM Interrupt Indication Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIF0 : BPWM Channel 0 Period Interrupt Status
This bit is set by hardware when BPWM0 counter reaches the requirement of interrupt (depend on PINTTYPE bit of PWM_INTEN register), software can write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
PIF1 : BPWM Channel 1 Period Interrupt Status
This bit is set by hardware when BPWM1 counter reaches the requirement of interrupt (depend on PINTTYPE bit of PWM_INTEN register), software can write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
DIF0 : BPWM Channel 0 Duty Interrupt Flag
Flag is set by hardware when channel 0 BPWM counter down count and reaches BPWM_CMPDAT 0, software can clear this bit by writing a one to it.
Note: If CMP equal to PERIOD, this flag is not working in Edge-aligned type selection
bits : 8 - 8 (1 bit)
access : read-write
DIF1 : BPWM Channel 1 Duty Interrupt Flag
Flag is set by hardware when channel 1 BPWM counter down count and reaches BPWM_CMPDAT 1, software can clear this bit by writing a one to it.
Note: If CMP equal to PERIOD, this flag is not working in Edge-aligned type selection
bits : 9 - 9 (1 bit)
access : read-write
Basic PWM Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN0 : PWM-timer 0 Enable Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding PWM-Timer stops running
#1 : 1
The corresponding PWM-Timer starts running
End of enumeration elements list.
PINV0 : PWM-timer 0 Output Polar Inverse Enable Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 output polar inverse Disabled
#1 : 1
PWM0 output polar inverse Enabled
End of enumeration elements list.
CMPINV0 : PWM-timer 0 Output Inverter Enable Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CNTMODE0 : PWM-timer 0 Auto-reload/One-shot Mode
Note: If there is a transition at this bit, it will cause BPWM_PERIOD0 and BPWM_CMPDAT0 be cleared.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-shot mode
#1 : 1
Auto-reload mode
End of enumeration elements list.
DTCNT01 : Dead-zone 0 Generator Enable Control
Note: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-zone 0 Generator Disabled
#1 : 1
Dead-zone 0 Generator Enabled
End of enumeration elements list.
CNTEN1 : PWM-timer 1 Enable Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-Timer Stopped
#1 : 1
Corresponding PWM-Timer Start Running
End of enumeration elements list.
PINV1 : PWM-timer 1 Output Polar Inverse Enable Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1 output polar inverse Disabled
#1 : 1
PWM1 output polar inverse Enabled
End of enumeration elements list.
CMPINV1 : PWM-timer 1 Output Inverter Enable Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CNTMODE1 : PWM-timer 1 Auto-reload/One-shot Mode
Note: If there is a transition at this bit, it will cause BPWM_PERIOD1 and BPWM_CMPDAT1 be cleared.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-shot mode
#1 : 1
Auto-reload mode
End of enumeration elements list.
BKODB0 : BPWM Channel 1 Brake Output Selection
Note: This bit effects BPWM0 only when BP0SYNEPWM is set
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0 output low when fault brake conditions asserted
#1 : 1
BPWM0 output high when fault brake conditions asserted
End of enumeration elements list.
BKODB1 : BPWM Channel 1 Brake Output Selection
Note: This bit effects BPWM1 only when BP1SYNEPWM is set
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM1 output low when fault brake conditions asserted
#1 : 1
BPWM1 output high when fault brake conditions asserted
End of enumeration elements list.
BP0SYNEPWM :
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#1 : 1
When EPWM enable will also enable BPWM0 at the same time
End of enumeration elements list.
BP1SYNEPWM :
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#1 : 1
When EPWM enable will also enable BPWM1 at the same time
End of enumeration elements list.
CNTTYPE01 : PWM01 Aligned Type Selection
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-aligned type
#1 : 1
Center-aligned type
End of enumeration elements list.
Basic PWM Period Counter Register 0
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Basic PWM Period Counter Register
PERIOD data determines the PWM period.
For Edge-aligned type:
Note: Any write to PERIOD will take effect in next PWM cycle.
Note: When PWM operating at Center-aligned type, PERIOD value should be set between 0x0000 to 0xFFFE. If PERIOD equal to 0xFFFF, the PWM will work unpredictable.
Note: When PERIOD value is set to 0, PWM output is always high.
bits : 0 - 15 (16 bit)
access : read-write
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