GDMA_CTL

GDMA_CSRC

GDMA_CDST

GDMA_CTCNT

GDMA_SRCB

GDMA_DSTB

GDMA_TCNT

GDMAEN : GDMA Enable. 0: Disables GDMA operation (default). 1: Enables GDMA operation this bit is cleared automatically when the transfer is complete to Disable mode. Note: The DMA transfer parameters must be programed before the module is enabled by this bit.
bits : 0 - 0 (1 bit)
access : read-write

GDMAMS : GDMA Mode Select 00: Software mode (Memory ( Memory APB ( Memory) (default). 01: External nXDREQ0 mode. USCI ( Memory. 10,11: Reserved
bits : 2 - 3 (2 bit)
access : read-write

DADIR : Destination Address Direction. 0: Destination address incremented successively (default). 1: Destination address decremented successively. Note: This bit must not be set to 1, if Burst Mode Enable (BME) bit is also set to 1.
bits : 4 - 4 (1 bit)
access : read-write

SADIR : Source Address Direction. 0: Source address incremented successively (default). 1: Source address decremented successively. Note: This bit must not be set to 1, if Burst Mode Enable (BME) bit is also set to 1.
bits : 5 - 5 (1 bit)
access : read-write

DAFIX : Destination Address Fixed. 0: Change the Destination address during the GDMA operation (default). 1: Do not change the Destination address during the GDMA operation. This feature can be used when data is transferred from a single address source to a memory area destination.
bits : 6 - 6 (1 bit)
access : read-write

SAFIX : Source Address Fixed. 0: Change the source address during the GDMA operation (default). 1: Do not change the source address during the GDMA operation. This feature can be used when data is transferred from a single address source to a memory area destination.
bits : 7 - 7 (1 bit)
access : read-write

GIEN : GDMA Interrupt Enable. 0: Do not generate an interrupt when the GDMA operation is finished (default). 1: An interrupt is generated when the GDMA operation is finished.
bits : 8 - 8 (1 bit)
access : read-write

BME : Burst Mode Enable. When this field is set to 1, TWS field must be set to '10' (32 bit double-word option), in addition the DMA initiation address must be 16-Bytes aligned. 0: Disables '4-data burst' mode. GDMA_TCNT is set to number of words to be transferred (default). 1: Enables '4-data burst' mode. GDMA_TCNT is set to number of words to be transferred, divided by 4.
bits : 9 - 9 (1 bit)
access : read-write

TWS : Transfer Width Select. The GDMA_SCRB and GDMA_DSTB must be set to be aligned with thedata width selected by this field. 00: One byte (8 bits) is transferred for every GDMA operation (default). 01: One word (16 bits) is transferred for every GDMA operation. 10: One double-word (32 bits) is transferred for every GDMA operation. 11: Reserved.
bits : 12 - 13 (2 bit)
access : read-write

SOFTTRG : Software Triggered GDMA. The firmware can request the GDMA transfer service by setting this bit to 1. This bit is cleared automatically by hardware when the transfer is complete. This bit is available only when GDMAMS field is 0. Note: When a GDMA transaction is in progress, writing to this field is illegal. 0: Ignored (default). 1: Request the GDMA transfer service.
bits : 16 - 16 (1 bit)
access : read-write

TCIF : Transfer complete Interrupt Flag. TCIF and GDMAERR can generate the GDMA interrupt. 0: The channel operation is in progress (default). 1: The channel operation ended this bit is set only by the GDMA hardware and is cleared by the firmware writing 0 to it.
bits : 18 - 18 (1 bit)
access : read-write

GDMAERR : GDMA Transfer Error. Indicates a transfer error occurred and generates the GDMA interrupt. 0: No error occurred (default). 1: The hardware sets this bit on a GDMA transfer failure.
bits : 20 - 20 (1 bit)
access : read-write

CurrentSrc : 32-bit Current Source Address. Indicates the source address where the GDMA transfer just occurred. During a block transfer, the GDMA determines the successive source addresses by adding to or subtracting from the source base address. Depending on the settings in the control register, the current source address remains the same, is incremented or is decremented.
bits : 0 - 31 (32 bit)
access : read-only

CurrentDst : 32-bit Current Destination Address. Indicates the destination address where the GDMA transfer just occurred. During a block transfer, the GDMA determines the successive destination addresses by adding to or subtracting from the destination base address. Depending on the settings in the control register, the current destination address remains the same, is incremented or is decremented.
bits : 0 - 31 (32 bit)
access : read-only

CurrentTfrCnt : Current Transfer Count.
bits : 0 - 12 (13 bit)
access : read-only

SrcBaseAddr : 32-bit Source Base Address. The GDMA channel starts reading its data from the source address as defined in this source base address register. During a block transfer, the GDMA determines successive destination addresses by adding to or subtracting from the source base address.
bits : 0 - 31 (32 bit)
access : read-write

DstBaseAddr : 32-bit Destination Base Address. The GDMA channel starts writing its data to the destination address, as defined in this register. During a block transfer, the GDMA determines successive destination addresses by adding to or subtracting from the destination base address.
bits : 0 - 31 (32 bit)
access : read-write

TfrCnt : 13-bit Transfer Count. Represents the required number of GDMA transfers. The maximum transfer count is 8K - 1.
bits : 0 - 12 (13 bit)
access : read-write