UUART_CTL

UUART_DATIN0

UUART_CTLIN0

UUART_CLKIN

UUART_LINECTL

UUART_TXDAT

UUART_RXDAT

UUART_BUFCTL

UUART_BUFSTS

UUART_INTEN

UUART_DMACTL

UUART_WKCTL

UUART_WKSTS

UUART_PROTCTL

UUART_PROTIEN

UUART_PROTSTS

UUART_BRGEN

FUNMODE : Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. Note: Other bit combinations are reserved.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYNCSEL : Input Signal Synchronization Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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ININV : Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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EDGEDET : Input Signal Edge Detection Mode This bit field selects which edge actives the trigger event of input data signal. Note: In UART function mode, it is suggested to set this bit field as 10.
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYNCSEL : Input Synchronization Signal Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ININV : Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYNCSEL : Input Synchronization Signal Selection This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LSB : LSB First Transmission Selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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DATOINV : Data Output Inverse Selection This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTLOINV : Control Signal Output Inverse Selection This bit defines the relation between the internal control signal and the output control signal. Note: In UART protocol, the control signal means nRTS signal.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DWIDTH : Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions [15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions [3:0]. 0x5: The data word contains 5 bits located at bit positions [4:0]. ... 0xF: The data word contains 15 bits located at bit positions [14:0]. Note: In UART protocol, the length can be configured as 6~13 bits.
bits : 8 - 11 (4 bit)
access : read-write

TXDAT : Transmit Data Software can use this bit field to write 16-bit transmit data for transmission.
bits : 0 - 15 (16 bit)
access : write-only

RXDAT : Received Data This bit field monitors the received data which stored in receive data buffer. Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).
bits : 0 - 15 (16 bit)
access : read-only

TXCLR : Clear Transmit Buffer Note: It is cleared automatically after one PCLK cycle.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

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RXOVIEN : Receive Buffer Overrun Error Interrupt Enable Control
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

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RXCLR : Clear Receive Buffer Note: It is cleared automatically after one PCLK cycle.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

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TXRST : Transmit Reset Note: It is cleared automatically after one PCLK cycle.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXRST : Receive Reset Note 1: It is cleared automatically after one PCLK cycle. Note 2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXEMPTY : Receive Buffer Empty Indicator
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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RXFULL : Receive Buffer Full Indicator
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVIF : Receive Buffer Over-run Error Interrupt Status This bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEMPTY : Transmit Buffer Empty Indicator
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

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TXFULL : Transmit Buffer Full Indicator
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

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TXSTIEN : Transmit Start Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit start event.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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TXENDIEN : Transmit End Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit finish event.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXSTIEN : Receive Start Interrupt Enable Bit This bit enables the interrupt generation in case of a receive start event.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

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RXENDIEN : Receive End Interrupt Enable Bit This bit enables the interrupt generation in case of a receive finish event.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

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DMARST : DMA Reset
bits : 0 - 0 (1 bit)
access : read-write

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TXDMAEN : DMA Transmit Channel Request Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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RXDMAEN : DMA Receive Channel Request Enable
bits : 2 - 2 (1 bit)
access : read-write

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DMAEN : DMA Mode Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

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WKEN : Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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PDBOPT : Power Down Blocking Option
bits : 2 - 2 (1 bit)
access : read-write

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WKF : Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

STOPB : Stop Bits This bit defines the number of stop bits in an UART frame.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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PARITYEN : Parity Enable Bit This bit defines the parity bit is enabled in an UART frame.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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EVENPARITY : Even Parity Enable Bit Note: This bit has effect only when PARITYEN is set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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ABREN : Auto-baud Rate Detect Enable Bit Note: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINBRKEN : LIN TX Break Mode Enable Control Note 1: When TX break field transfer operation is finished, this bit will be cleared automatically. Note 2: 13-bit level 0 and 1-bit level 1 were sent out before the 1st data be transmitted.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINRXEN : LIN RX Duplex Mode Enable Control Note: This bit is used to check the break duration for incoming data when the LIN operation is active.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

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DATWKEN : Data Wake-up Mode Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKECNT : Wake-up Counter These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode.
bits : 11 - 14 (4 bit)
access : read-write

BRDETITV : Baud Rate Detection Interval This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set. Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
bits : 16 - 24 (9 bit)
access : read-write

STICKEN : Stick Parity Enable Bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCEN : Transmit Break Control Enable Bit Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PROTEN : UART Protocol Enable Bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

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BRKIEN : LIN Break Detected Interrupt Enable Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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ABRIEN : Auto-baud Rate Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLSIEN : Receive Line Status Interrupt Enable Bit Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXSTIF : Transmit Start Interrupt Flag Note 1: It is cleared by software writing one into this bit. Note 2: Used for user to load next transmit data when there is no data in transmit buffer.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXENDIF : Transmit End Interrupt Flag Note: It is cleared by software writing one into this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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RXSTIF : Receive Start Interrupt Flag Note: It is cleared by software writing one into this bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

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RXENDIF : Receive End Interrupt Flag Note: It is cleared by software writing one into this bit.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PARITYERR : Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FRMERR : Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

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BREAK : Break Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits). Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKDETIF : LIN Break Detected Interrupt Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than 12-bit transmission time in LIN mode function. Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRDETIF : Auto-baud Rate Interrupt Flag This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 3 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. Note: This bit can be cleared by writing '1' to it.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXBUSY : RX Bus Status Flag (Read Only) This bit indicates the busy status of the receiver.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABERRSTS : Auto-baud Rate Error Status This bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again. Note 1: This bit is set at the same time of ABRDETIF. Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RCLKSEL : Reference Clock Source Selection This bit selects the source signal of reference clock (fREF_CLK).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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PTCLKSEL : Protocol Clock Source Selection This bit selects the source signal of protocol clock (fPROT_CLK).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPCLKSEL : Sample Clock Source Selection This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
bits : 2 - 3 (2 bit)
access : read-write

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End of enumeration elements list.

TMCNTEN : Timing Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter.
bits : 4 - 4 (1 bit)
access : read-write

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TMCNTSRC : Timing Measurement Counter Clock Source Selection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDSCNT : Pre-divider for Sample Counter
bits : 8 - 9 (2 bit)
access : read-write

DSCNT : Denominator for Sample Counter This bit field defines the divide ratio of the sample clock fSAMP_CLK. Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
bits : 10 - 14 (5 bit)
access : read-write

CLKDIV : Clock Divider Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
bits : 16 - 25 (10 bit)
access : read-write