UI2C_CTL

UI2C_LINECTL

UI2C_TXDAT

UI2C_RXDAT

UI2C_BUFSTS

UI2C_DMACTL

UI2C_DEVADDR0

UI2C_ADDRMSK0

UI2C_WKCTL

UI2C_WKSTS

UI2C_PROTCTL

UI2C_PROTIEN

UI2C_PROTSTS

UI2C_BRGEN

UI2C_TMCTL

FUNMODE : Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE. Note: Other bit combinations are reserved.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LSB : LSB First Transmission Selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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DWIDTH : Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions [15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions [3:0]. 0x5: The data word contains 5 bits located at bit positions [4:0]. ... 0xF: The data word contains 15 bits located at bit positions [14:0]. Note: In I2C protocol, the length must be configured as 8 bits.
bits : 8 - 11 (4 bit)
access : read-write

TXDAT : Transmit Data Software can use this bit field to write 8-bit transmit data for transmission.
bits : 0 - 7 (8 bit)
access : write-only

GDMASTO : I2C STOP Control (for GDMA only)
bits : 14 - 14 (1 bit)
access : write-only

GDMASTA : I2C START Control (for GDMA only) Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
bits : 15 - 15 (1 bit)
access : write-only

RXDAT : Received Data This bit field monitors the received data which stored in receive data buffer. Note 1: In I2C protocol, only use RXDAT[7:0].
bits : 0 - 15 (16 bit)
access : read-only

RXEMPTY : Receive Buffer Empty Indicator
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

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RXFULL : Receive Buffer Full Indicator
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

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TXEMPTY : Transmit Buffer Empty Indicator
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

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TXFULL : Transmit Buffer Full Indicator
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

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DMARST : DMA Reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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TXDMAEN : DMA Transmit Channel Request Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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RXDMAEN : DMA Receive Channel Request Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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DMAEN : DMA Mode Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

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NACKEN : 1: When finish of RXDAM in slave mode, hardware will auto NACK the last byte.
bits : 4 - 4 (1 bit)
access : read-write

STOPEN : 1: When finish of RXDAM in master mode, hardware will auto generate STOP condition
bits : 5 - 5 (1 bit)
access : read-write

DEVADDR : Device Address In I2C protocol, this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0]. Note: When I2C operating in 7-bit address mode, only use DEVADDR[6:0]
bits : 0 - 9 (10 bit)
access : read-write

ADDRMSK : USCI Device Address Mask USCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to 0, that means the received corresponding register bit should be exact the same as address register.
bits : 0 - 9 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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WKADDREN : Wake-up Address Match Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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WKF : Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

GCFUNC : General Call Function
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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AA : Assert Acknowledge Control
bits : 1 - 1 (1 bit)
access : read-write

STO : I2C STOP Control
bits : 2 - 2 (1 bit)
access : read-write

STA : I2C START Control Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
bits : 3 - 3 (1 bit)
access : read-write

ADDR10EN : Address 10-bit Function Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

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PTRG : I2C Protocol Trigger When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

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SCLOUTEN : SCL Output Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

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MONEN : I2C Monitor Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

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TOCNT : Time-out Clock Cycle This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.
bits : 16 - 25 (10 bit)
access : read-write

PROTEN : I2C Protocol Enable Bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

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TOIEN : Time-out Interrupt Enable Control In I2C protocol, this bit enables the interrupt generation in case of a time-out event.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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STARIEN : Start Condition Received Interrupt Enable Control This bit enables the generation of a protocol interrupt if a start condition is detected.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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STORIEN : Stop Condition Received Interrupt Enable Control This bit enables the generation of a protocol interrupt if a stop condition is detected.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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NACKIEN : Non - Acknowledge Interrupt Enable Control This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

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ARBLOIEN : Arbitration Lost Interrupt Enable Control This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

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ERRIEN : Error Interrupt Enable Control This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

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ACKIEN : Acknowledge Interrupt Enable Control This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
bits : 6 - 6 (1 bit)
access : read-write

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TOIF : Time-out Interrupt Flag Note: It is cleared by software writing one into this bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

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ONBUSY : On Bus Busy Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

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STARIF : Start Condition Received Interrupt Flag This bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode. It is cleared by software writing one into this bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

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STORIF : Stop Condition Received Interrupt Flag It is cleared by software writing one into this bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

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NACKIF : Non - Acknowledge Received Interrupt Flag It is cleared by software writing one into this bit Note: When this bit is set, the master will generate a stop bit in next transmation, so MCU needs to clear it before transmition.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ARBLOIF : Arbitration Lost Interrupt Flag It is cleared by software writing one into this bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

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ERRIF : Error Interrupt Flag It is cleared by software writing one into this bit Note: This bit is set when slave mode, user must write one into STO register to the defined 'not addressed' slave mode.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

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ACKIF : Acknowledge Received Interrupt Flag It is cleared by software writing one into this bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

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SLASEL : Slave Select Status This bit indicates that this device has been selected as slave. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

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SLAREAD : Slave Read Request Status This bit indicates that a slave read request has been detected. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

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WKAKDONE : Wakeup Address Frame Acknowledge Bit Done Note: This bit can't release when WKUPIF is set.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

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WRSTSWK : Read/Write Status Bit in Address Wakeup Frame
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

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BUSHANG : Bus Hang-up This bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal. Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

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RCLKSEL : Reference Clock Source Selection This bit selects the source signal of reference clock (fREF_CLK).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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PTCLKSEL : Protocol Clock Source Selection This bit selects the source signal of protocol clock (fPROT_CLK).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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SPCLKSEL : Sample Clock Source Selection This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMCNTEN : Time Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMCNTSRC : Time Measurement Counter Clock Source Selection In I2C mode, this bit need clear to 0 to do timeout measurement counter with fPCLK.
bits : 5 - 5 (1 bit)
access : read-write

CLKDIV : Clock Divider Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate.
bits : 16 - 25 (10 bit)
access : read-write

STCTL : Setup Time Configure Control Register This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.
bits : 0 - 5 (6 bit)
access : read-write

HTCTL : Hold Time Configure Control Register This field is used to generate the delay timing between SCL falling edge SDA edge in transmission mode.
bits : 6 - 11 (6 bit)
access : read-write