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ADC

Peripheral Memory Blocks

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x80 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :

Registers

ADC_CS_CTL (CS_CTL)

ADC_CTL (CTL)

ADC_TRGSOR (TRGSOR)

ADC_TRGDLY (TRGDLY)

ADC_SMPCNT (SMPCNT)

ADC_STATUS (STATUS)

ADC_VALSTS (VALSTS)

ADC0_DAT0

ADC0_DAT1

ADC0_DAT2

ADC0_DAT3

ADC0_DAT4

ADC0_DAT5

ADC0_DAT6

ADC0_DAT7

ADC0_DAT8

ADC0_DAT9

ADC0_DAT10

ADC0_DAT11

ADC0_DAT12

ADC0_DAT13

ADC0_DAT14

ADC0_DAT15

ADC1_DAT0

ADC1_DAT1

ADC1_DAT2

ADC1_DAT3

ADC1_DAT4

ADC1_DAT5

ADC1_DAT6

ADC1_DAT7

ADC1_DAT8

ADC1_DAT9

ADC1_DAT10

ADC1_DAT11

ADC1_DAT12

ADC1_DAT13

ADC1_DAT14

ADC1_DAT15


ADC_CS_CTL (CS_CTL)

ADC Channel Select Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CS_CTL ADC_CS_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC0CSEN ADC1CSEN

ADC0CSEN : ADC0(SH0) Channel Select Enable
bits : 0 - 15 (16 bit)
access : read-write

ADC1CSEN : ADC1(SH1) Channel Select Enable
bits : 16 - 31 (16 bit)
access : read-write


ADC_CTL (CTL)

ADC Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CTL ADC_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCEN ADC0IEN ADC0HWTRGEN ADC0SWTRG ADCMODE ADC1IEN ADC1HWTRGEN ADC1SWTRG

ADCEN : ADC Converter Enable Bit Note: Before starting the A/D conversion function, this bit should be set to '1'. Clear it to '0' to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable ADC Converter

#1 : 1

Enable ADC Converter

End of enumeration elements list.

ADC0IEN : ADC0 Interrupt Enable Bit Note: If ADC0IEN bit is set to 1 the ADC0_INT is requested by the end of ADC conversion.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable ADC0 interrupt

#1 : 1

Enable ADC0 interrupt

End of enumeration elements list.

ADC0HWTRGEN : Hardware Trigger ADC Convertion Enable Bit Enable or disable triggering of A/D conversion by Hardware (PWM, Timer, ECAP and ADC self)
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable ADC0 hardware trigger function

#1 : 1

Enable ADC0 hardware trigger function

End of enumeration elements list.

ADC0SWTRG : ADC0 Conversion Start Note: ADC0SWTRG will be set to '1' when any of ADC0 trigger event happen or user also can write '1' to this bit to demand a software ADC0 trigger, when hardware finish the conversion it will be cleared to '0' automatically.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion stopped and A/D converter entered idle state

#1 : 1

Start ADC0 and indicate there has ADC0 conversion request

End of enumeration elements list.

ADCMODE : A/D Conversion Mode
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Independent Mode, independent trigger function and independent interrupt

#01 : 1

Reserved.

#10 : 2

Simultaneous Mode, simultaneously triggered by ADC0, ADC0 and ADC1 convert sequentially then only interrupt ADC0IF is generated

#11 : 3

Simultaneous Mode, simultaneously triggered by ADC0, ADC0 and ADC1 convert sequentially then only interrupt ADC0IF is generated

End of enumeration elements list.

ADC1IEN : ADC1 Interrupt Enable Control Note: If ADC1IEN bit is set to 1 the ADC1_INT is requested by the end of ADC conversion.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable ADC1 interrupt

#1 : 1

Enable ADC1 interrupt

End of enumeration elements list.

ADC1HWTRGEN : Hardware Trigger ADC Conversion Enable Control Enable or disable triggering of A/D conversion by Hardware (PWM, Timer, ECAP and ADC self)
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable ADC1 hardware trigger function

#1 : 1

Enable ADC1 hardware trigger function

End of enumeration elements list.

ADC1SWTRG : ADC1 Conversion Start Note: ADC1SWTRG will be set to '1' when any of ADC1 trigger event happen or user also can write '1' to this bit to demand a software ADC1 trigger, when hardware finish the conversion it will be cleared to '0' automatically.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion stopped and A/D converter entered idle state

#1 : 1

Start ADC1 and indicate there has ADC1 conversion request

End of enumeration elements list.


ADC_TRGSOR (TRGSOR)

ADC Hardware Trigger Source Control Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_TRGSOR ADC_TRGSOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC0TRGSOR ADC0PWMTRGSEL ADC0STADCSEL ADC1TRGSOR ADC1PWMTRGSEL ADC1STADCSEL

ADC0TRGSOR : ADC0 Trigger Source
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

STADC

#0001 : 1

PWM0

#0010 : 2

PWM1

#0011 : 3

PWM2

#0100 : 4

PWM3

#0101 : 5

PWM4

#0110 : 6

PWM5

#0111 : 7

TMR0_MATCH. (refer to Figure 6.61 Timer Controller Block Diagram)

#1000 : 8

TMR1_MATCH. (refer to Figure 6.61 Timer Controller Block Diagram)

#1001 : 9

ECAPPHG_TRG. (From ECAP, CPAEN (CAPTF0| CAPTF1| CAPTF2)

#1010 : 10

ADC0IF

#1011 : 11

ADC1IF

End of enumeration elements list.

ADC0PWMTRGSEL : PWM Trigger Selection for ADC0
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

EPWM Signal Falling. (Not available in edge-aligned type)

#01 : 1

EPWM Counter Central. (Not available in edge-aligned type)

#10 : 2

EPWM signal Rising

#11 : 3

Period

End of enumeration elements list.

ADC0STADCSEL : ADC0 External Trigger Pin (STADC) Trigger Selection
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Rising

#01 : 1

Falling

#10 : 2

Rising or Falling

#11 : 3

Reserved.

End of enumeration elements list.

ADC1TRGSOR : ADC1 Trigger Source
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0

STADC

#0001 : 1

PWM0

#0010 : 2

PWM1

#0011 : 3

PWM2

#0100 : 4

PWM3

#0101 : 5

PWM4

#0110 : 6

PWM5

#0111 : 7

TMR0_MATCH. (refer to Figure 6.61 Timer Controller Block Diagram)

#1000 : 8

TMR1_MATCH. (refer to Figure 6.61 Timer Controller Block Diagram)

#1001 : 9

ECAPPHG_TRG. (From ECAP, CPAEN (CAPTF0| CAPTF1| CAPTF2)

#1010 : 10

ADC0IF

#1011 : 11

ADC1IF

End of enumeration elements list.

ADC1PWMTRGSEL : PWM Trigger Selection for ADC1
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

EPWM Signal Falling. (Not available in edge-aligned type)

#01 : 1

EPWM Counter Central. (Not available in edge-aligned type)

#10 : 2

EPWM signal Rising

#11 : 3

Period

End of enumeration elements list.

ADC1STADCSEL : ADC1 External Trigger Pin (STADC) Trigger Selection
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 0

Rising

#01 : 1

Falling

#10 : 2

Rising or Falling

#11 : 3

Reserved.

End of enumeration elements list.


ADC_TRGDLY (TRGDLY)

ADC Trigger Delay Control Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_TRGDLY ADC_TRGDLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC0DELAY ADC1DELAY

ADC0DELAY : ADC0 Trigger Delay Timer Setting this field will insert a delay time from H/W tirgger condition happens to conversion starts Delay time is (4 * ADC0DELAY) * system clock Note: Software trigger does not support delay-time insertion.
bits : 0 - 7 (8 bit)
access : read-write

ADC1DELAY : ADC1 Trigger Delay Timer Setting this field will insert a delay time from H/W tirgger condition happens to conversion starts Delay time is (4 * ADC1DELAY) * system clock Note: Software trigger does not support delay-time insertion.
bits : 16 - 23 (8 bit)
access : read-write


ADC_SMPCNT (SMPCNT)

ADC Sampling Time Counter Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_SMPCNT ADC_SMPCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCSMPCNT

ADCSMPCNT : ADC Sampling Counter For normal channel:
bits : 0 - 3 (4 bit)
access : read-write


ADC_STATUS (STATUS)

ADC Status Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STATUS ADC_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC0IF ADC0BUSY ADC0CH ADC1IF ADC1BUSY ADC1CH ADC0EOC ADC1EOC

ADC0IF : A/D Conversion End Flag A status flag that indicates the end of A/D conversion. ADF is set to '1' When A/D conversion ends. This flag can be cleared by writing '1' to itself.
bits : 0 - 0 (1 bit)
access : read-write

ADC0BUSY : BUSY/IDLE
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

A/D converter is in idle state

#1 : 1

A/D converter is busy at conversion

End of enumeration elements list.

ADC0CH : Current Conversion Channel It is read only.
bits : 4 - 7 (4 bit)
access : read-write

ADC1IF : ADC1 Conversion End Flag A status flag that indicates the end of A/D conversion. ADF is set to '1' When A/D conversion ends. This flag can be cleared by writing '1' to itself.
bits : 8 - 8 (1 bit)
access : read-write

ADC1BUSY : BUSY/IDLE
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

A/D converter is in idle state

#1 : 1

A/D converter is busy at conversion

End of enumeration elements list.

ADC1CH : Current Conversion Channel It is read only.
bits : 12 - 15 (4 bit)
access : read-write

ADC0EOC : ADC0 end of convert.
bits : 23 - 23 (1 bit)
access : read-write

ADC1EOC : ADC1 end of convert.
bits : 31 - 31 (1 bit)
access : read-write


ADC_VALSTS (VALSTS)

ADC Valid Status Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_VALSTS ADC_VALSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC0VALID ADC1VALID

ADC0VALID : Bits set 1 when ADC0 CHn convertion is finished, and it is automatically cleared when ADC0_DATn is read.
bits : 0 - 15 (16 bit)
access : read-write

ADC1VALID : Bits set 1 when ADC1 CHn convertion is finished, and it is automatically cleared when ADC1_DATn is read.
bits : 16 - 31 (16 bit)
access : read-write


ADC0_DAT0

ADC0 Data Register n
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT0 ADC0_DAT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC0DAT

ADC0DAT : ADC0 Conversion Result This field contains conversion result of ADC0_CHn.
bits : 0 - 11 (12 bit)
access : read-only


ADC0_DAT1

ADC0 Data Register n
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT1 ADC0_DAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT2

ADC0 Data Register n
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT2 ADC0_DAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT3

ADC0 Data Register n
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT3 ADC0_DAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT4

ADC0 Data Register n
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT4 ADC0_DAT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT5

ADC0 Data Register n
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT5 ADC0_DAT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT6

ADC0 Data Register n
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT6 ADC0_DAT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT7

ADC0 Data Register n
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT7 ADC0_DAT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT8

ADC0 Data Register n
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT8 ADC0_DAT8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT9

ADC0 Data Register n
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT9 ADC0_DAT9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT10

ADC0 Data Register n
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT10 ADC0_DAT10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT11

ADC0 Data Register n
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT11 ADC0_DAT11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT12

ADC0 Data Register n
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT12 ADC0_DAT12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT13

ADC0 Data Register n
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT13 ADC0_DAT13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT14

ADC0 Data Register n
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT14 ADC0_DAT14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC0_DAT15

ADC0 Data Register n
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0_DAT15 ADC0_DAT15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT0

ADC1 Data Register n
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT0 ADC1_DAT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC1DAT

ADC1DAT : ADC1 Conversion Result This field contains conversion result of ADC1_CHn.
bits : 0 - 11 (12 bit)
access : read-only


ADC1_DAT1

ADC1 Data Register n
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT1 ADC1_DAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT2

ADC1 Data Register n
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT2 ADC1_DAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT3

ADC1 Data Register n
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT3 ADC1_DAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT4

ADC1 Data Register n
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT4 ADC1_DAT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT5

ADC1 Data Register n
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT5 ADC1_DAT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT6

ADC1 Data Register n
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT6 ADC1_DAT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT7

ADC1 Data Register n
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT7 ADC1_DAT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT8

ADC1 Data Register n
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT8 ADC1_DAT8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT9

ADC1 Data Register n
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT9 ADC1_DAT9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT10

ADC1 Data Register n
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT10 ADC1_DAT10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT11

ADC1 Data Register n
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT11 ADC1_DAT11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT12

ADC1 Data Register n
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT12 ADC1_DAT12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT13

ADC1 Data Register n
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT13 ADC1_DAT13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT14

ADC1 Data Register n
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT14 ADC1_DAT14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC1_DAT15

ADC1 Data Register n
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1_DAT15 ADC1_DAT15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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