\n
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x80 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :
ADC Channel Select Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0CSEN : ADC0(SH0) Channel Select Enable
bits : 0 - 15 (16 bit)
access : read-write
ADC1CSEN : ADC1(SH1) Channel Select Enable
bits : 16 - 31 (16 bit)
access : read-write
ADC Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCEN : ADC Converter Enable Bit
Note: Before starting the A/D conversion function, this bit should be set to '1'. Clear it to '0' to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ADC Converter
#1 : 1
Enable ADC Converter
End of enumeration elements list.
ADC0IEN : ADC0 Interrupt Enable Bit
Note: If ADC0IEN bit is set to 1 the ADC0_INT is requested by the end of ADC conversion.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ADC0 interrupt
#1 : 1
Enable ADC0 interrupt
End of enumeration elements list.
ADC0HWTRGEN : Hardware Trigger ADC Convertion Enable Bit
Enable or disable triggering of A/D conversion by Hardware (PWM, Timer, ECAP and ADC self)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ADC0 hardware trigger function
#1 : 1
Enable ADC0 hardware trigger function
End of enumeration elements list.
ADC0SWTRG : ADC0 Conversion Start
Note: ADC0SWTRG will be set to '1' when any of ADC0 trigger event happen or user also can write '1' to this bit to demand a software ADC0 trigger, when hardware finish the conversion it will be cleared to '0' automatically.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion stopped and A/D converter entered idle state
#1 : 1
Start ADC0 and indicate there has ADC0 conversion request
End of enumeration elements list.
ADCMODE : A/D Conversion Mode
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Independent Mode, independent trigger function and independent interrupt
#01 : 1
Reserved.
#10 : 2
Simultaneous Mode, simultaneously triggered by ADC0, ADC0 and ADC1 convert sequentially then only interrupt ADC0IF is generated
#11 : 3
Simultaneous Mode, simultaneously triggered by ADC0, ADC0 and ADC1 convert sequentially then only interrupt ADC0IF is generated
End of enumeration elements list.
ADC1IEN : ADC1 Interrupt Enable Control
Note: If ADC1IEN bit is set to 1 the ADC1_INT is requested by the end of ADC conversion.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ADC1 interrupt
#1 : 1
Enable ADC1 interrupt
End of enumeration elements list.
ADC1HWTRGEN : Hardware Trigger ADC Conversion Enable Control
Enable or disable triggering of A/D conversion by Hardware (PWM, Timer, ECAP and ADC self)
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ADC1 hardware trigger function
#1 : 1
Enable ADC1 hardware trigger function
End of enumeration elements list.
ADC1SWTRG : ADC1 Conversion Start
Note: ADC1SWTRG will be set to '1' when any of ADC1 trigger event happen or user also can write '1' to this bit to demand a software ADC1 trigger, when hardware finish the conversion it will be cleared to '0' automatically.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion stopped and A/D converter entered idle state
#1 : 1
Start ADC1 and indicate there has ADC1 conversion request
End of enumeration elements list.
ADC Hardware Trigger Source Control Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0TRGSOR : ADC0 Trigger Source
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
STADC
#0001 : 1
PWM0
#0010 : 2
PWM1
#0011 : 3
PWM2
#0100 : 4
PWM3
#0101 : 5
PWM4
#0110 : 6
PWM5
#0111 : 7
TMR0_MATCH. (refer to Figure 6.61 Timer Controller Block Diagram)
#1000 : 8
TMR1_MATCH. (refer to Figure 6.61 Timer Controller Block Diagram)
#1001 : 9
ECAPPHG_TRG. (From ECAP, CPAEN (CAPTF0| CAPTF1| CAPTF2)
#1010 : 10
ADC0IF
#1011 : 11
ADC1IF
End of enumeration elements list.
ADC0PWMTRGSEL : PWM Trigger Selection for ADC0
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
EPWM Signal Falling. (Not available in edge-aligned type)
#01 : 1
EPWM Counter Central. (Not available in edge-aligned type)
#10 : 2
EPWM signal Rising
#11 : 3
Period
End of enumeration elements list.
ADC0STADCSEL : ADC0 External Trigger Pin (STADC) Trigger Selection
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Rising
#01 : 1
Falling
#10 : 2
Rising or Falling
#11 : 3
Reserved.
End of enumeration elements list.
ADC1TRGSOR : ADC1 Trigger Source
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
STADC
#0001 : 1
PWM0
#0010 : 2
PWM1
#0011 : 3
PWM2
#0100 : 4
PWM3
#0101 : 5
PWM4
#0110 : 6
PWM5
#0111 : 7
TMR0_MATCH. (refer to Figure 6.61 Timer Controller Block Diagram)
#1000 : 8
TMR1_MATCH. (refer to Figure 6.61 Timer Controller Block Diagram)
#1001 : 9
ECAPPHG_TRG. (From ECAP, CPAEN (CAPTF0| CAPTF1| CAPTF2)
#1010 : 10
ADC0IF
#1011 : 11
ADC1IF
End of enumeration elements list.
ADC1PWMTRGSEL : PWM Trigger Selection for ADC1
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
EPWM Signal Falling. (Not available in edge-aligned type)
#01 : 1
EPWM Counter Central. (Not available in edge-aligned type)
#10 : 2
EPWM signal Rising
#11 : 3
Period
End of enumeration elements list.
ADC1STADCSEL : ADC1 External Trigger Pin (STADC) Trigger Selection
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Rising
#01 : 1
Falling
#10 : 2
Rising or Falling
#11 : 3
Reserved.
End of enumeration elements list.
ADC Trigger Delay Control Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0DELAY : ADC0 Trigger Delay Timer
Setting this field will insert a delay time from H/W tirgger condition happens to conversion starts
Delay time is (4 * ADC0DELAY) * system clock
Note: Software trigger does not support delay-time insertion.
bits : 0 - 7 (8 bit)
access : read-write
ADC1DELAY : ADC1 Trigger Delay Timer
Setting this field will insert a delay time from H/W tirgger condition happens to conversion starts
Delay time is (4 * ADC1DELAY) * system clock
Note: Software trigger does not support delay-time insertion.
bits : 16 - 23 (8 bit)
access : read-write
ADC Sampling Time Counter Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCSMPCNT : ADC Sampling Counter
For normal channel:
bits : 0 - 3 (4 bit)
access : read-write
ADC Status Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0IF : A/D Conversion End Flag
A status flag that indicates the end of A/D conversion.
ADF is set to '1' When A/D conversion ends.
This flag can be cleared by writing '1' to itself.
bits : 0 - 0 (1 bit)
access : read-write
ADC0BUSY : BUSY/IDLE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D converter is in idle state
#1 : 1
A/D converter is busy at conversion
End of enumeration elements list.
ADC0CH : Current Conversion Channel
It is read only.
bits : 4 - 7 (4 bit)
access : read-write
ADC1IF : ADC1 Conversion End Flag
A status flag that indicates the end of A/D conversion.
ADF is set to '1' When A/D conversion ends.
This flag can be cleared by writing '1' to itself.
bits : 8 - 8 (1 bit)
access : read-write
ADC1BUSY : BUSY/IDLE
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D converter is in idle state
#1 : 1
A/D converter is busy at conversion
End of enumeration elements list.
ADC1CH : Current Conversion Channel
It is read only.
bits : 12 - 15 (4 bit)
access : read-write
ADC0EOC : ADC0 end of convert.
bits : 23 - 23 (1 bit)
access : read-write
ADC1EOC : ADC1 end of convert.
bits : 31 - 31 (1 bit)
access : read-write
ADC Valid Status Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0VALID : Bits set 1 when ADC0 CHn convertion is finished, and it is automatically cleared when ADC0_DATn is read.
bits : 0 - 15 (16 bit)
access : read-write
ADC1VALID : Bits set 1 when ADC1 CHn convertion is finished, and it is automatically cleared when ADC1_DATn is read.
bits : 16 - 31 (16 bit)
access : read-write
ADC0 Data Register n
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADC0DAT : ADC0 Conversion Result
This field contains conversion result of ADC0_CHn.
bits : 0 - 11 (12 bit)
access : read-only
ADC0 Data Register n
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0 Data Register n
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADC1DAT : ADC1 Conversion Result
This field contains conversion result of ADC1_CHn.
bits : 0 - 11 (12 bit)
access : read-only
ADC1 Data Register n
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1 Data Register n
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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