\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
Analog Comparator 0 Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACMPEN : Comparator Enable Control
Note: Comparator output needs to wait 2 us stable time after ACMPEN is set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Comparator Disabled
#1 : 1
Comparator Enabled
End of enumeration elements list.
ACMPIE : Comparator Interrupt Enable Control
Note1: Interrupt is generated if ACMPIE bit is set to '1' after ACMP conversion is finished.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP interrupt function Disabled
#1 : 1
ACMP interrupt function Enabled
End of enumeration elements list.
ACMPHYSEN : Comparator0 Hysteresis Enable Control
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
ACMP0 Hysteresis function Disabled (Default)
#01 : 1
ACMP0 Hysteresis function at comparator0 that the typical range is 20mV
#10 : 2
ACMP0 Hysteresis function at comparator0 that the typical range is 90mV
#11 : 3
ACMP0 Hysteresis function at comparator0 that the typical range is 150mV
End of enumeration elements list.
EDGESEL : Interrupt Flag Trigger Edge Detection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Interrupt Flag Trigger Edge Disabled
#01 : 1
Rising
#10 : 2
Falling
#11 : 3
Rising/Falling
End of enumeration elements list.
PBRKSEL : ACMP to EPWM Brake Selection
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP Result direct output
#1 : 1
ACMP Delay Trigger Result output
End of enumeration elements list.
DLYTRGSEL : Analog Comparator Delay Trigger Mode Trigger Level Selection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Analog Comparator Delay Trigger Mode Trigger Disabled
#01 : 1
High
#10 : 2
Low
#11 : 3
High/Low
End of enumeration elements list.
DLYTRGSOR : Analog Comparator Delay Trigger Mode Trigger Source Selection
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
EPWM_CH0
#01 : 1
EPWM_CH2
#10 : 2
EPWM_CH4
#11 : 3
TMR2_MATCH
End of enumeration elements list.
DLYTRGEN : Analog Comparator Delay Trigger Mode Enable Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator Delay Trigger Mode Disabled
#1 : 1
Analog Comparator Delay Trigger Mode Enabled
End of enumeration elements list.
DLYTRGIE : Analog Comparator Delay Trigger Mode Interrupt Enable Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator Delay Trigger Mode Interrupt Disabled
#1 : 1
Analog Comparator Delay Trigger Mode Interrupt Enabled
End of enumeration elements list.
DLYEDGESEL : PWM Delay Trigger Interrupt Flag Trigger Edge Detection
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Interrupt Flag Trigger Edge Disabled
#01 : 1
Rising
#10 : 2
Falling
#11 : 3
Rising/Falling
End of enumeration elements list.
POLARITY : Analog Comparator Polarity Control
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator normal output
#1 : 1
Analog Comparator invert output
End of enumeration elements list.
NFCLKS : Noise Filter Clock Pre-divided Selection
To determine the sampling frequency of the Noise Filter clock
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
PCLK
#001 : 1
PCLK / 2
#010 : 2
PCLK / 4
#011 : 3
PCLK / 8
#100 : 4
PCLK/ 16
#101 : 5
PCLK / 32
#110 : 6
PCLK / 64
#111 : 7
PCLK / 256
End of enumeration elements list.
NFDIS : Disable Comparator Noise Filter
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter Enabled
#1 : 1
Noise filter Disabled
End of enumeration elements list.
CPNSEL : Comparator Negative Input Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
ACMP0_N (PB.4)
#01 : 1
Band_Gap
#10 : 2
DAC1
#11 : 3
DAC0
End of enumeration elements list.
CPPSEL : Comparator Positive Input Select
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#000 : 0
ACMP0_P0 (PB.0)
#001 : 1
ACMP0_P1 (PB.1)
#010 : 2
ACMP0_P2 (PB.2)
#011 : 3
ACMP0_P3 (PC.1)
#100 : 4
OP1_O (PE.2)
End of enumeration elements list.
PRESET : Comparator Result Preset Value
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
0 for ACMP0 preset value
#1 : 1
1 for ACMP0 preset value
End of enumeration elements list.
Analog Comparator Delay Trigger Mode Dleay Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELAY : Analog Comparator Delay Trigger Mode Delay cycle(PCLK*cycle)
bits : 0 - 8 (9 bit)
access : read-write
DAC Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAC0 : DAC0 Referance Voltage (VDD x DAC0[11:0]/4096)
bits : 0 - 11 (12 bit)
access : read-write
DAC1 : DAC1 Referance Voltage (VDD x DAC1[11:0]/4096)
bits : 16 - 27 (12 bit)
access : read-write
DAC Buffer Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAC0BUFEN : DAC0 Output Amplifier Enable Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Amplifier Disabled
#1 : 1
Amplifier Enabled
End of enumeration elements list.
DAC1BUFEN : DAC1 Output Amplifier Enable Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Amplifier Disabled
#1 : 1
Amplifier Enabled
End of enumeration elements list.
Analog Comparator Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACMPF0 : Comparator0 Flag
This bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if ACMPIE set.
Write '1' to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
ACMPO0 : Comparator0 Output
bits : 2 - 2 (1 bit)
access : read-write
DLYTRGF0 : Comparator0 Flag
This bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if DLYTRGIEN set.
Write '1' to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
DLYTRGO0 : Analog Comparator0 Delay Trigger Mode Comparator Output
bits : 6 - 6 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.