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CLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x54 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x70 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

CLK_PWRCTL (PWRCTL)

CLK_CLKSEL0 (CLKSEL0)

CLK_CLKSEL1 (CLKSEL1)

CLK_CLKDIV0 (CLKDIV0)

CLK_CLKSEL2 (CLKSEL2)

CLK_PLLCTL (PLLCTL)

CLK_CLKOCTL (CLKOCTL)

CLK_APBCLK1 (APBCLK1)

CLK_CLKSEL3 (CLKSEL3)

CLK_AHBCLK (AHBCLK)

CLK_BODCLK (BODCLK)

CLK_LXTCTL (LXTCTL)

CLK_CLKDCTL (CLKDCTL)

CLK_CLKDSTS (CLKDSTS)

CLK_CDUPB (CDUPB)

CLK_CDLOWB (CDLOWB)

CLK_APBCLK0 (APBCLK0)

CLK_STATUS (STATUS)


CLK_PWRCTL (PWRCTL)

System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PWRCTL CLK_PWRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTEN LXTEN HIRCEN LIRCEN PDWKDLY PDWKIEN PDWKIF PDEN HXTGAIN HXTMD

HXTEN : HXT Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~24 MHz External High Speed Crystal (HXT) Disabled

#1 : 1

4~24 MHz External High Speed Crystal (HXT) Enabled

End of enumeration elements list.

LXTEN : LXT Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz External Low Speed Crystal (LXT) Disabled

#1 : 1

32.768 kHz External Low Speed Crystal (LXT) Enabled

End of enumeration elements list.

HIRCEN : HIRC Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

48 MHz internal high speed RC oscillator (HIRC) Disabled

#1 : 1

48 MHz internal high speed RC oscillator (HIRC) Enabled

End of enumeration elements list.

LIRCEN : LIRC Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

10 kHz internal low speed RC oscillator (LIRC) Disabled

#1 : 1

10 kHz internal low speed RC oscillator (LIRC) Enabled

End of enumeration elements list.

PDWKDLY : Enable the Wake-up Delay Counter (Write Protect) When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal oscillator (HXT) and 512 clock cycles when chip works at 48 MHz internal high speed RC oscillator (HIRC). Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock cycles delay Disabled

#1 : 1

Clock cycles delay Enabled

End of enumeration elements list.

PDWKIEN : Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power-down mode wake-up interrupt Disabled

#1 : 1

Power-down mode wake-up interrupt Enabled

End of enumeration elements list.

PDWKIF : Power-down Mode Wake-up Interrupt Status Set by 'Power-down wake-up event', which indicates that resume from Power-down mode' The flag is set if the EINT0~5, VDET, GPIO, USBD, UART0~1, WDT, BOD, TMR0~3 or I2C0~1 wake-up occurred. Note 1: This bit can be cleared by software writing 1. Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) is set to 1.
bits : 6 - 6 (1 bit)
access : read-write

PDEN : System Power-down Enable (Write Protect) When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. When chip wakes up from Power-down mode, this bit is automatically cleared. Users need to set this bit again for next Power-down. In Power-down mode, HXT and HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. In Power-down mode, the PLL and system clock are disabled, and the clock source selection is ignored. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip operating normally or chip in idle mode because of WFI command

#1 : 1

Chip waits CPU sleep command WFI and then enters Power-down mode

End of enumeration elements list.

HXTGAIN : HXT Gain Control Bit (Write Protect) Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 10 - 12 (3 bit)
access : read-write

Enumeration:

#000 : 0

HXT frequency is from 4 MHz to 8 MHz

#001 : 1

HXT frequency is from 8 MHz to 12 MHz

#010 : 2

HXT frequency is from 12 MHz to 16 MHz

#011 : 3

HXT frequency is from 16 MHz to 24 MHz

End of enumeration elements list.

HXTMD : HXT Bypass Mode (Write Protect) Note 2: This bit is write protected. Refer to the SYS_REGCTL register.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

HXT work as crystal mode. PF.2 and PF.3 are configured as external high speed crystal (HXT) pins

#1 : 1

HXT works as external clock mode. PF.3 is configured as external clock input pin

End of enumeration elements list.


CLK_CLKSEL0 (CLKSEL0)

Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL0 CLK_CLKSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKSEL STCLKSEL PCLK0SEL PCLK1SEL

HCLKSEL : HCLK Clock Source Selection (Write Protect) Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT

#001 : 1

Clock source from LXT

#010 : 2

Clock source from PLL/2 clock

#011 : 3

Clock source from LIRC

#100 : 4

Clock source from HIRC

#111 : 7

Clock source from HIRC/2 clock

End of enumeration elements list.

STCLKSEL : Cortex-M23 SysTick Clock Source Selection (Write Protect) Note 2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT

#001 : 1

Clock source from LXT

#010 : 2

Clock source from HXT/2

#011 : 3

Clock source from HCLK/2

#111 : 7

Clock source from HIRC/4

End of enumeration elements list.

PCLK0SEL : PCLK0 Clock Source Selection (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

APB0 BUS clock source from HCLK

#1 : 1

APB0 BUS clock source from HCLK/2

End of enumeration elements list.

PCLK1SEL : PCLK1 Clock Source Selection (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

APB1 BUS clock source from HCLK

#1 : 1

APB1 BUS clock source from HCLK/2

End of enumeration elements list.


CLK_CLKSEL1 (CLKSEL1)

Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL1 CLK_CLKSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTSEL ADCSEL TMR0SEL TMR1SEL TMR2SEL TMR3SEL UART0SEL UART1SEL

WDTSEL : Watchdog Timer Clock Source Selection (Write Protect) Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Reserved.

#01 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock

#10 : 2

Clock source from HCLK/2048 clock

#11 : 3

Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock

End of enumeration elements list.

ADCSEL : ADC Clock Source Selection
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock

#01 : 1

Clock source from PLL

#10 : 2

Clock source from PCLK0

#11 : 3

Clock source from HIRC/2 clock

End of enumeration elements list.

TMR0SEL : TIMER0 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock

#010 : 2

Clock source from PCLK0

#011 : 3

Clock source from external clock T0 pin

#101 : 5

Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock

#111 : 7

Clock source from HIRC/2 clock

End of enumeration elements list.

TMR1SEL : TIMER1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock

#010 : 2

Clock source from PCLK0

#011 : 3

Clock source from external clock T1 pin

#101 : 5

Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock

#111 : 7

Clock source from HIRC/2 clock

End of enumeration elements list.

TMR2SEL : TIMER2 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock

#010 : 2

Clock source from PCLK1

#011 : 3

Clock source from external clock T2 pin

#101 : 5

Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock

#111 : 7

Clock source from HIRC/2 clock

End of enumeration elements list.

TMR3SEL : TIMER3 Clock Source Selection
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock

#010 : 2

Clock source from PCLK1

#011 : 3

Clock source from external clock T3 pin

#101 : 5

Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock

#111 : 7

Clock source from HIRC/2 clock

End of enumeration elements list.

UART0SEL : UART0 Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock

#01 : 1

Clock source from PLL/2 clock

#10 : 2

Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock

#11 : 3

Clock source from HIRC/2 clock

End of enumeration elements list.

UART1SEL : UART1 Clock Source Selection
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock

#01 : 1

Clock source from PLL/2 clock

#10 : 2

Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock

#11 : 3

Clock source from HIRC/2 clock

End of enumeration elements list.


CLK_CLKDIV0 (CLKDIV0)

Clock Divider Number Register 0
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDIV0 CLK_CLKDIV0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKDIV USBDIV UART0DIV UART1DIV ADCDIV

HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write

USBDIV : USB Clock Divide Number From PLL Source Note: If the HIRC is selected, it is delivery to USB clock directly.
bits : 4 - 7 (4 bit)
access : read-write

UART0DIV : UART0 Clock Divide Number From UART0 Clock Source
bits : 8 - 11 (4 bit)
access : read-write

UART1DIV : UART1 Clock Divide Number From UART1 Clock Source
bits : 12 - 15 (4 bit)
access : read-write

ADCDIV : ADC Clock Divide Number From ADC Clock Source
bits : 16 - 23 (8 bit)
access : read-write


CLK_CLKSEL2 (CLKSEL2)

Clock Source Select Control Register 2
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL2 CLK_CLKSEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKOSEL WWDTSEL SPI0SEL SPI1SEL

CLKOSEL : Clock Divider Clock Source Selection
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock

#010 : 2

Clock source from HCLK

#011 : 3

Clock source from HIRC/2 clock

#100 : 4

Clock source from SOF (USB start of frame event)

#101 : 5

Clock source from HIRC clock

End of enumeration elements list.

WWDTSEL : Window Watchdog Timer Clock Source Selection
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#10 : 2

Clock source from HCLK/2048 clock

#11 : 3

Clock source from 10 kHz internal low speed RC oscillator (LIRC)

End of enumeration elements list.

SPI0SEL : SPI0 Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock

#01 : 1

Clock source from PLL/2 clock

#10 : 2

Clock source from PCLK0

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.

SPI1SEL : SPI1 Clock Source Selection
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock

#01 : 1

Clock source from PLL/2 clock

#10 : 2

Clock source from PCLK0

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.


CLK_PLLCTL (PLLCTL)

PLL Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PLLCTL CLK_PLLCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBDIV INDIV OUTDIV PD BP OE PLLSRC STBSEL

FBDIV : PLL Feedback Divider Control Refer to the formulas below the table.
bits : 0 - 8 (9 bit)
access : read-write

INDIV : PLL Input Divider Control Refer to the formulas below the table.
bits : 9 - 13 (5 bit)
access : read-write

OUTDIV : PLL Output Divider Control Refer to the formulas below the table.
bits : 14 - 15 (2 bit)
access : read-write

PD : Power-down Mode If set PDEN(CLK_PWRCTL[7]) bit to 1, the PLL will enter Power-down mode, too.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in normal mode

#1 : 1

PLL is in Power-down mode (default)

End of enumeration elements list.

BP : PLL Bypass Control
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in normal mode (default)

#1 : 1

PLL clock output is same as PLL input clock FIN

End of enumeration elements list.

OE : PLL OUT Enable Control
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL FOUT Enabled

#1 : 1

PLL FOUT is fixed low

End of enumeration elements list.

PLLSRC : PLL Source Clock Selection
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL source clock from external 4~24 MHz high-speed crystal (HXT)

#1 : 1

PLL source clock from 48 MHz internal high-speed oscillator divided by 2 (HIRC/2)

End of enumeration elements list.

STBSEL : PLL Stable Counter Selection
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL stable time is 6144 PLL source clock (suitable for source clock equal to or less than 12 MHz)

#1 : 1

PLL stable time is 12288 PLL source clock (suitable for source clock greater than 12 MHz)

End of enumeration elements list.


CLK_CLKOCTL (CLKOCTL)

Clock Output Control Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKOCTL CLK_CLKOCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQSEL CLKOEN DIV1EN

FREQSEL : Clock Output Frequency Selection The formula of output frequency is Fin is the input clock frequency. Fout is the frequency of divider output clock. N is the 4-bit value of FREQSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

CLKOEN : Clock Output Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock Output function Disabled

#1 : 1

Clock Output function Enabled

End of enumeration elements list.

DIV1EN : Clock Output Divide One Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock Output will output clock with source frequency divided by FREQSEL

#1 : 1

Clock Output will output clock with source frequency

End of enumeration elements list.


CLK_APBCLK1 (APBCLK1)

APB Devices Clock Enable Control Register 1
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_APBCLK1 CLK_APBCLK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLSI0CKEN LLSI1CKEN LLSI2CKEN LLSI3CKEN LLSI4CKEN LLSI5CKEN LLSI6CKEN LLSI7CKEN LLSI8CKEN LLSI9CKEN

LLSI0CKEN : LLSI0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

LLSI0 clock Disabled

#1 : 1

LLSI0 clock Enabled

End of enumeration elements list.

LLSI1CKEN : LLSI1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

LLSI1 clock Disabled

#1 : 1

LLSI1 clock Enabled

End of enumeration elements list.

LLSI2CKEN : LLSI2 Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

LLSI2 clock Disabled

#1 : 1

LLSI2 clock Enabled

End of enumeration elements list.

LLSI3CKEN : LLSI3 Clock Enable Bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

LLSI3 clock Disabled

#1 : 1

LLSI3 clock Enabled

End of enumeration elements list.

LLSI4CKEN : LLSI4 Clock Enable Bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

LLSI4 clock Disabled

#1 : 1

LLSI4 clock Enabled

End of enumeration elements list.

LLSI5CKEN : LLSI5 Clock Enable Bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

LLSI5 clock Disabled

#1 : 1

LLSI5 clock Enabled

End of enumeration elements list.

LLSI6CKEN : LLSI6 Clock Enable Bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

LLSI6 clock Disabled

#1 : 1

LLSI6 clock Enabled

End of enumeration elements list.

LLSI7CKEN : LLSI7 Clock Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

LLSI7 clock Disabled

#1 : 1

LLSI7 clock Enabled

End of enumeration elements list.

LLSI8CKEN : LLSI8 Clock Enable Bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

LLSI8 clock Disabled

#1 : 1

LLSI8 clock Enabled

End of enumeration elements list.

LLSI9CKEN : LLSI9 Clock Enable Bit
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

LLSI9 clock Disabled

#1 : 1

LLSI9 clock Enabled

End of enumeration elements list.


CLK_CLKSEL3 (CLKSEL3)

Clock Source Select Control Register 3
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL3 CLK_CLKSEL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBDSEL

USBDSEL : USBD Clock Source Selection (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from HIRC clock

#1 : 1

Clock source from PLL clock

End of enumeration elements list.


CLK_AHBCLK (AHBCLK)

AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_AHBCLK CLK_AHBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMACKEN ISPCKEN CRCCKEN FMCIDLE GPIOACKEN GPIOBCKEN GPIOCCKEN GPIODCKEN GPIOFCKEN

PDMACKEN : PDMA Controller Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA peripheral clock Disabled

#1 : 1

PDMA peripheral clock Enabled

End of enumeration elements list.

ISPCKEN : Flash ISP Controller Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Flash ISP peripheral clock Disabled

#1 : 1

Flash ISP peripheral clock Enabled

End of enumeration elements list.

CRCCKEN : CRC Generator Controller Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRC peripheral clock Disabled

#1 : 1

CRC peripheral clock Enabled

End of enumeration elements list.

FMCIDLE : Flash Memory Controller Clock Enable Bit in IDLE Mode
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

FMC peripheral clock Disabled when chip operating at IDLE mode

#1 : 1

FMC peripheral clock Enabled when chip operating at IDLE mode

End of enumeration elements list.

GPIOACKEN : General Purpose I/O PA Group Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO PA group clock Disabled

#1 : 1

GPIO PA group clock Enabled

End of enumeration elements list.

GPIOBCKEN : General Purpose I/O PB Group Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO PB group clock Disabled

#1 : 1

GPIO PB group clock Enabled

End of enumeration elements list.

GPIOCCKEN : General Purpose I/O PC Group Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO PC group clock Disabled

#1 : 1

GPIO PC group clock Enabled

End of enumeration elements list.

GPIODCKEN : General Purpose I/O PD Group Clock Enable Bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO PD group clock Disabled

#1 : 1

GPIO PD group clock Enabled

End of enumeration elements list.

GPIOFCKEN : General Purpose I/O PF Group Clock Enable Bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO PF group clock Disabled

#1 : 1

GPIO PF group clock Enabled

End of enumeration elements list.


CLK_BODCLK (BODCLK)

Clock Source Select for BOD Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_BODCLK CLK_BODCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDETCKSEL

VDETCKSEL : Clock Source Selection for Voltage Detector The Voltage Detector clock source for detecting external input voltage is defined by VDETCKSEL. Note 1: If LIRC is selected, LIRCEN (CLK_PWRCTL[3]) must be enabled. Note 2: If LXT is selected, LXTEN (CLK_PWRCTL[1]) must be enabled. Note 3: This bit is also used for Brown-out detector clock source.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source is from 10 kHz internal low speed RC oscillator (LIRC) clock

#1 : 1

Clock source is from 32.768 kHz external low speed crystal oscillator (LXT) clock

End of enumeration elements list.


CLK_LXTCTL (LXTCTL)

LXT Control Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_LXTCTL CLK_LXTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAIN

GAIN : Oscillator Gain Option User can select oscillator gain according to crystal external loading and operating temperature range. The greater gain value corresponding to stronger driving capability and higher power consumption.
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

#000 : 0

L0 mode (ESR=35K CL =25pF)

#001 : 1

L1 mode (ESR=35K CL =25pF)

#010 : 2

L2 mode (ESR=35K CL =25pF)

#011 : 3

L3 mode (ESR=70K CL =25pF)

#100 : 4

L4 mode (ESR=70K CL =25pF)

#101 : 5

L5 mode (ESR=70K CL =25pF)

#110 : 6

L6 mode (ESR=90K CL =25pF)

#111 : 7

L7 mode (ESR=90K CL =25pF)

End of enumeration elements list.


CLK_CLKDCTL (CLKDCTL)

Clock Fail Detector Control Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDCTL CLK_CLKDCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTFDEN HXTFIEN LXTFDEN LXTFIEN HXTFQDEN HXTFQIEN

HXTFDEN : HXT Clock Fail Detector Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock Fail detector Disabled

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) clock Fail detector Enabled

End of enumeration elements list.

HXTFIEN : HXT Clock Fail Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock Fail interrupt Disabled

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) clock Fail interrupt Enabled

End of enumeration elements list.

LXTFDEN : LXT Clock Fail Detector Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock Fail detector Disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) clock Fail detector Enabled

End of enumeration elements list.

LXTFIEN : LXT Clock Fail Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock Fail interrupt Disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) clock Fail interrupt Enabled

End of enumeration elements list.

HXTFQDEN : HXT Clock Frequency Monitor Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled

End of enumeration elements list.

HXTFQIEN : HXT Clock Frequency Monitor Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled

End of enumeration elements list.


CLK_CLKDSTS (CLKDSTS)

Clock Fail Detector Status Register
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDSTS CLK_CLKDSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTFIF LXTFIF HXTFQIF

HXTFIF : HXT Clock Fail Interrupt Flag (Write Protect) Note 1: This bit can be cleared to 0 by software writing 1. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock normal

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) clock stop

End of enumeration elements list.

LXTFIF : LXT Clock Fail Interrupt Flag (Write Protect) Note 1: This bit can be cleared to 0 by software writing 1. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock normal

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) stop

End of enumeration elements list.

HXTFQIF : HXT Clock Frequency Monitor Interrupt Flag (Write Protect) Note 1: This bit can be cleared to 0 by software writing 1. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock normal

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) clock frequency abnormal

End of enumeration elements list.


CLK_CDUPB (CDUPB)

Clock Frequency Detector Upper Boundary Register
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CDUPB CLK_CDUPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPERBD

UPERBD : HXT Clock Frequency Detector Upper Boundary The bits define the high value of frequency monitor window. When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will be set to 1. Note: The frequency out of range will be asserted when HIRC_period*1024 HXT_period*CLK_DUPB or HIRC_period*1024 HXT_period*CLK_CDLOWB.
bits : 0 - 9 (10 bit)
access : read-write


CLK_CDLOWB (CDLOWB)

Clock Frequency Detector Low Boundary Register
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CDLOWB CLK_CDLOWB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWERBD

LOWERBD : HXT Clock Frequency Detector Low Boundary The bits define the low value of frequency monitor window. When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will be set to 1. Note: The frequency out of range will be asserted when HIRC_period*1024 HXT_period*CLK_DUPB or HIRC_period*1024 HXT_period*CLK_CDLOWB.
bits : 0 - 9 (10 bit)
access : read-write


CLK_APBCLK0 (APBCLK0)

APB Devices Clock Enable Control Register 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_APBCLK0 CLK_APBCLK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTCKEN TMR0CKEN TMR1CKEN TMR2CKEN TMR3CKEN CLKOCKEN I2C0CKEN I2C1CKEN SPI0CKEN SPI1CKEN UART0CKEN UART1CKEN BPWM0CKEN BPWM1CKEN BPWM2CKEN BPWM3CKEN USBDCKEN ADCCKEN

WDTCKEN : Watchdog Timer Clock Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog Timer Clock Disabled

#1 : 1

Watchdog Timer Clock Enabled

End of enumeration elements list.

TMR0CKEN : Timer0 Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer0 Clock Disabled

#1 : 1

Timer0 Clock Enabled

End of enumeration elements list.

TMR1CKEN : Timer1 Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer1 Clock Disabled

#1 : 1

Timer1 Clock Enabled

End of enumeration elements list.

TMR2CKEN : Timer2 Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer2 Clock Disabled

#1 : 1

Timer2 Clock Enabled

End of enumeration elements list.

TMR3CKEN : Timer3 Clock Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer3 Clock Disabled

#1 : 1

Timer3 Clock Enabled

End of enumeration elements list.

CLKOCKEN : CLKO Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

CLKO Clock Disabled

#1 : 1

CLKO Clock Enabled

End of enumeration elements list.

I2C0CKEN : I2C0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 Clock Disabled

#1 : 1

I2C0 Clock Enabled

End of enumeration elements list.

I2C1CKEN : I2C1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 Clock Disabled

#1 : 1

I2C1 Clock Enabled

End of enumeration elements list.

SPI0CKEN : SPI0 Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 Clock Disabled

#1 : 1

SPI0 Clock Enabled

End of enumeration elements list.

SPI1CKEN : SPI1 Clock Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI1 Clock Disabled

#1 : 1

SPI1 Clock Enabled

End of enumeration elements list.

UART0CKEN : UART0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 clock Disabled

#1 : 1

UART0 clock Enabled

End of enumeration elements list.

UART1CKEN : UART1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 clock Disabled

#1 : 1

UART1 clock Enabled

End of enumeration elements list.

BPWM0CKEN : BPWM0 Clock Enable Bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM0 clock Disabled

#1 : 1

BPWM0 clock Enabled

End of enumeration elements list.

BPWM1CKEN : BPWM1 Clock Enable Bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM1 clock Disabled

#1 : 1

BPWM1 clock Enabled

End of enumeration elements list.

BPWM2CKEN : BPWM2 Clock Enable Bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM2 clock Disabled

#1 : 1

BPWM2 clock Enabled

End of enumeration elements list.

BPWM3CKEN : BPWM3 Clock Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM3 clock Disabled

#1 : 1

BPWM3 clock Enabled

End of enumeration elements list.

USBDCKEN : USB Device Clock Enable Bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

USB Device clock Disabled

#1 : 1

USB Device clock Enabled

End of enumeration elements list.

ADCCKEN : Analog-digital-converter Clock Enable Bit
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADC clock Disabled

#1 : 1

ADC clock Enabled

End of enumeration elements list.


CLK_STATUS (STATUS)

Clock Status Monitor Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLK_STATUS CLK_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTSTB LXTSTB PLLSTB LIRCSTB HIRCSTB CLKSFAIL

HXTSTB : HXT Clock Source Stable Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled

End of enumeration elements list.

LXTSTB : LXT Clock Source Stable Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled

End of enumeration elements list.

PLLSTB : Internal PLL Clock Source Stable Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal PLL clock is not stable or disabled

#1 : 1

Internal PLL clock is stable and enabled

End of enumeration elements list.

LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled

#1 : 1

10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled

End of enumeration elements list.

HIRCSTB : HIRC Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

HIRC clock is not stable or disabled

#1 : 1

HIRC clock is stable and enabled

End of enumeration elements list.

CLKSFAIL : Clock Switching Fail Flag (Read Only) This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1. Note: After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Clock switching success

#1 : 1

Clock switching failure

End of enumeration elements list.



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