Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x70 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x80 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
address_offset : 0xB0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xC0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
address_offset : 0xF0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x140 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x200 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x340 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection :
PA I/O Mode Control
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE0 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE1 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE2 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE3 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE4 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE5 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE6 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE7 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE8 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE9 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE10 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE11 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE12 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE13 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE14 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
MODE15 : Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px.n is in Input mode
#01 : 1
Px.n is in Push-pull Output mode
#10 : 2
Px.n is in Open-drain Output mode
#11 : 3
Px.n is in Quasi-bidirectional mode
End of enumeration elements list.
PA Pin Value
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIN0 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 0 - 0 (1 bit)
access : read-only
PIN1 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 1 - 1 (1 bit)
access : read-only
PIN2 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 2 - 2 (1 bit)
access : read-only
PIN3 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 3 - 3 (1 bit)
access : read-only
PIN4 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 4 - 4 (1 bit)
access : read-only
PIN5 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 5 - 5 (1 bit)
access : read-only
PIN6 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 6 - 6 (1 bit)
access : read-only
PIN7 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 7 - 7 (1 bit)
access : read-only
PIN8 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 8 - 8 (1 bit)
access : read-only
PIN9 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 9 - 9 (1 bit)
access : read-only
PIN10 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 10 - 10 (1 bit)
access : read-only
PIN11 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 11 - 11 (1 bit)
access : read-only
PIN12 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 12 - 12 (1 bit)
access : read-only
PIN13 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 13 - 13 (1 bit)
access : read-only
PIN14 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 14 - 14 (1 bit)
access : read-only
PIN15 : Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 15 - 15 (1 bit)
access : read-only
PA De-bounce Enable Control
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBEN0 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN1 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN2 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN3 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN4 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN5 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN6 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN7 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN8 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN9 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN10 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN11 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN12 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN13 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN14 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
DBEN15 : Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n de-bounce function Disabled
#1 : 1
Px.n de-bounce function Enabled
End of enumeration elements list.
PF I/O Mode Control
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Digital Input Path Disable Control
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Data Output Value
address_offset : 0x148 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Data Output Write Mask
address_offset : 0x14C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Pin Value
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF De-bounce Enable Control
address_offset : 0x154 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Interrupt Trigger Type Control
address_offset : 0x158 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Interrupt Enable Control
address_offset : 0x15C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Interrupt Source Flag
address_offset : 0x160 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Input Schmitt Trigger Enable
address_offset : 0x164 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF High Slew Rate Control
address_offset : 0x168 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF High Drive Strength Control
address_offset : 0x16C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF Pull-up Selection Register
address_offset : 0x170 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA Interrupt Trigger Type Control
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE0 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE1 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE2 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE3 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE4 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE5 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE6 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE7 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE8 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE9 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE10 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE11 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE12 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE13 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE14 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
TYPE15 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
Interrupt De-bounce Control
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBCLKSEL : De-bounce Sampling Cycle Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Sample interrupt input once per 1 clocks
#0001 : 1
Sample interrupt input once per 2 clocks
#0010 : 2
Sample interrupt input once per 4 clocks
#0011 : 3
Sample interrupt input once per 8 clocks
#0100 : 4
Sample interrupt input once per 16 clocks
#0101 : 5
Sample interrupt input once per 32 clocks
#0110 : 6
Sample interrupt input once per 64 clocks
#0111 : 7
Sample interrupt input once per 128 clocks
#1000 : 8
Sample interrupt input once per 256 clocks
#1001 : 9
Sample interrupt input once per 2*256 clocks
#1010 : 10
Sample interrupt input once per 4*256 clocks
#1011 : 11
Sample interrupt input once per 8*256 clocks
#1100 : 12
Sample interrupt input once per 16*256 clocks
#1101 : 13
Sample interrupt input once per 32*256 clocks
#1110 : 14
Sample interrupt input once per 64*256 clocks
#1111 : 15
Sample interrupt input once per 128*256 clocks
End of enumeration elements list.
DBCLKSRC : De-bounce Counter Clock Source Selection
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
De-bounce counter clock source is the HCLK
#1 : 1
De-bounce counter clock source is the internal 10 kHz internal low speed oscillator
End of enumeration elements list.
ICLKON : Interrupt Clock on Mode
Note: It is recommended to disable this bit to save system power if no special application concern.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1
#1 : 1
All I/O pins edge detection circuit is always active after reset
End of enumeration elements list.
PA Interrupt Enable Control
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLIEN0 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN1 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN2 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN3 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN4 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN5 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN6 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN7 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN8 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN9 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN10 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN11 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN12 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN13 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN14 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
FLIEN15 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level low or high to low interrupt Disabled
#1 : 1
Px.n level low or high to low interrupt Enabled
End of enumeration elements list.
RHIEN0 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN1 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN2 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN3 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN4 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN5 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN6 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN7 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN8 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN9 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN10 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN11 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN12 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN13 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN14 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
RHIEN15 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n level high or low to high interrupt Disabled
#1 : 1
Px.n level high or low to high interrupt Enabled
End of enumeration elements list.
PA Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTSRC0 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC1 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC2 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC3 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC4 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC5 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC6 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC7 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC8 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC9 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC10 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC11 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC12 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC13 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC14 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
INTSRC15 : Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action.
No interrupt at Px.n
#1 : 1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
End of enumeration elements list.
GPIO PA.n Pin Data Input/Output
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDIO : GPIO Px.n Pin Data Input/Output
Writing this bit can control one GPIO pin output value.
Read this register to get GPIO pin status.
For example, writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]), reading PA0_PDIO will return the value of PIN (PA_PIN[0]).
Note 1: The writing operation will not be affected by register DATMSK (Px_DATMSK[n]).
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding GPIO pin set to low
#1 : 1
Corresponding GPIO pin set to high
End of enumeration elements list.
GPIO PA.n Pin Data Input/Output
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x214 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x218 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x21C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x220 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x224 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x228 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x22C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x230 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x234 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x238 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x23C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA Input Schmitt Trigger Enable
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMTEN0 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN1 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN2 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN3 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN4 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN5 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN6 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN7 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN8 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN9 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN10 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN11 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN12 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN13 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN14 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
SMTEN15 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n input schmitt trigger function Disabled
#1 : 1
Px.n input schmitt trigger function Enabled
End of enumeration elements list.
GPIO PB.n Pin Data Input/Output
address_offset : 0x240 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x244 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x248 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x24C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x250 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x254 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x258 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x25C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x260 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x264 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x268 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x26C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x270 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x274 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x278 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.n Pin Data Input/Output
address_offset : 0x27C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA High Slew Rate Control
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSREN0 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN1 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN2 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN3 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN4 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN5 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN6 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN7 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN8 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN9 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN10 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN11 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN12 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN13 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN14 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
HSREN15 : Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic slew rate
#1 : 1
Px.n output with higher slew rate
End of enumeration elements list.
GPIO PC.n Pin Data Input/Output
address_offset : 0x280 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x284 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x288 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x28C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x290 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x294 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x298 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x29C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x2A0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x2A4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x2A8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x2AC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x2B0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x2B4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x2B8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.n Pin Data Input/Output
address_offset : 0x2BC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA High Drive Strength Control
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HDRVEN0 : Port A and F Pin[n] Driving Strength Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN1 : Port A and F Pin[n] Driving Strength Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN2 : Port A and F Pin[n] Driving Strength Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN3 : Port A and F Pin[n] Driving Strength Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN4 : Port A and F Pin[n] Driving Strength Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN5 : Port A and F Pin[n] Driving Strength Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN6 : Port A and F Pin[n] Driving Strength Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN7 : Port A and F Pin[n] Driving Strength Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN8 : Port A and F Pin[n] Driving Strength Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN9 : Port A and F Pin[n] Driving Strength Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN10 : Port A and F Pin[n] Driving Strength Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN11 : Port A and F Pin[n] Driving Strength Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN12 : Port A and F Pin[n] Driving Strength Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN13 : Port A and F Pin[n] Driving Strength Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN14 : Port A and F Pin[n] Driving Strength Control
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
HDRVEN15 : Port A and F Pin[n] Driving Strength Control
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n output with basic driving and sink strength
#1 : 1
Px.n output with high driving and sink strength
End of enumeration elements list.
GPIO PD.n Pin Data Input/Output
address_offset : 0x2C0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2C4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2C8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2CC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2D0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2D4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2D8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2DC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2E0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2E4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2E8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2EC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2F0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2F4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2F8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.n Pin Data Input/Output
address_offset : 0x2FC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA Pull-up Selection Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUSEL0 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL1 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL2 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL3 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL4 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL5 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL6 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL7 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL8 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL9 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL10 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL11 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL12 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL13 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL14 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
PUSEL15 : Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n pull-up disable
#1 : 1
Px.n pull-up enable
End of enumeration elements list.
GPIO PF.n Pin Data Input/Output
address_offset : 0x340 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x344 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x348 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x34C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x350 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x354 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x358 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x35C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x360 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x364 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x368 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x36C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x370 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x374 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x378 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PF.n Pin Data Input/Output
address_offset : 0x37C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA Digital Input Path Disable Control
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DINOFF0 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF1 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF2 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF3 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF4 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF5 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF6 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF7 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF8 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF9 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF10 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF11 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF12 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF13 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF14 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
DINOFF15 : Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n digital input path Enabled
#1 : 1
Px.n digital input path Disabled (digital input tied to low)
End of enumeration elements list.
PB I/O Mode Control
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Digital Input Path Disable Control
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Data Output Value
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Pin Value
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB De-bounce Enable Control
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Interrupt Trigger Type Control
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Interrupt Enable Control
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Interrupt Source Flag
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Input Schmitt Trigger Enable
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB High Slew Rate Control
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB Pull-up Selection Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT0 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT1 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT2 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT3 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT4 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT5 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT6 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT7 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT8 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT9 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT10 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT11 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT12 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT13 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT14 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT15 : Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
PC I/O Mode Control
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Digital Input Path Disable Control
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Data Output Value
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Pin Value
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC De-bounce Enable Control
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Interrupt Trigger Type Control
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Interrupt Enable Control
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Interrupt Source Flag
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Input Schmitt Trigger Enable
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC High Slew Rate Control
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC Pull-up Selection Register
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA Data Output Write Mask
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATMSK0 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK1 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK2 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK3 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK4 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK5 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK6 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK7 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK8 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK9 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK10 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK11 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK12 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK13 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK14 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
DATMSK15 : Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#1 : 1
Corresponding DOUT (Px_DOUT[n]) bit protected
End of enumeration elements list.
PD I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Digital Input Path Disable Control
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Data Output Value
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Pin Value
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD De-bounce Enable Control
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Interrupt Trigger Type Control
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Interrupt Enable Control
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Interrupt Source Flag
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Input Schmitt Trigger Enable
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD High Slew Rate Control
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD Pull-up Selection Register
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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