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PDMA_DSCT1_FIRST (DSCT1_FIRST)
PDMA_DSCT2_FIRST (DSCT2_FIRST)
PDMA_DSCT3_FIRST (DSCT3_FIRST)
PDMA_DSCT4_FIRST (DSCT4_FIRST)
PDMA_DSCT5_FIRST (DSCT5_FIRST)
PDMA_DSCT6_FIRST (DSCT6_FIRST)
PDMA_DSCT7_FIRST (DSCT7_FIRST)
PDMA_DSCT8_FIRST (DSCT8_FIRST)
PDMA_DSCT9_FIRST (DSCT9_FIRST)
PDMA_DSCT0_FIRST (DSCT0_FIRST)
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPMODE : PDMA Operation Mode Selection
Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Idle state: Channel is stopped or this table is complete. When PDMA finishes channel table task, OPMODE will be cleared to idle state automatically
#01 : 1
Basic mode: The descriptor table only has one task. When this task is finished, the TDIF(PDMA_INTSTS[1]) will be asserted
#10 : 2
Scatter-Gather mode: When operating in this mode, user must give the first descriptor table address in PDMA_DSCT_FIRST register the PDMA controller will ignore this task, then load the next task to execute
#11 : 3
Reserved.
End of enumeration elements list.
TXTYPE : Transfer Type
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Burst transfer type
#1 : 1
Single transfer type
End of enumeration elements list.
BURSIZE : Burst Size
This field is used for peripheral to determine the burst size or used to determine the re-arbitration size.
Note: This field is only useful in burst transfer type.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
128 Transfers
#001 : 1
64 Transfers
#010 : 2
32 Transfers
#011 : 3
16 Transfers
#100 : 4
8 Transfers
#101 : 5
4 Transfers
#110 : 6
2 Transfers
#111 : 7
1 Transfers
End of enumeration elements list.
TBINTDIS : Table Interrupt Disable Bit
This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.
Note: If this bit set to '1', the TEMPTYF will not be set.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Table interrupt Enabled
#1 : 1
Table interrupt Disabled
End of enumeration elements list.
SAINC : Source Address Increment
This Field Is Used To Set The Source Address Increment Size.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#11 : 3
No Increment (Fixed Address)
End of enumeration elements list.
DAINC : Destination Address Increment
This field is used to set the destination address increment size.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#11 : 3
No increment (fixed address)
End of enumeration elements list.
TXWIDTH : Transfer Width Selection
This field is used for transfer width.
Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example, if source address is 0x2000_0202, but TXWIDTH is word transfer, the source address is not word alignment. The source address is aligned when TXWIDTH is byte or half-word transfer.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
One byte (8 bit) is transferred for every operation
#01 : 1
One half-word (16 bit) is transferred for every operation
#10 : 2
One word (32-bit) is transferred for every operation
#11 : 3
Reserved.
End of enumeration elements list.
TXCNT : Transfer Count
The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
Note: When PDMA finishes each transfer data, this field will be decreased immediately.
bits : 16 - 29 (14 bit)
access : read-write
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset of PDMA Channel n
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset of PDMA Channel n
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset of PDMA Channel n
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : PDMA Transfer Source Address Register
This field indicates a 32-bit source address of PDMA controller.
bits : 0 - 31 (32 bit)
access : read-write
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Channel Control Register
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0 : PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN1 : PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN2 : PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN3 : PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN4 : PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN5 : PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN6 : PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN7 : PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN8 : PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN9 : PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
PDMA Transfer Pause Control Register
address_offset : 0x404 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PAUSE0 : PDMA Channel n Transfer Pause Control Register (Write Only)
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE1 : PDMA Channel n Transfer Pause Control Register (Write Only)
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE2 : PDMA Channel n Transfer Pause Control Register (Write Only)
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE3 : PDMA Channel n Transfer Pause Control Register (Write Only)
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE4 : PDMA Channel n Transfer Pause Control Register (Write Only)
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE5 : PDMA Channel n Transfer Pause Control Register (Write Only)
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE6 : PDMA Channel n Transfer Pause Control Register (Write Only)
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE7 : PDMA Channel n Transfer Pause Control Register (Write Only)
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE8 : PDMA Channel n Transfer Pause Control Register (Write Only)
bits : 8 - 8 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE9 : PDMA Channel n Transfer Pause Control Register (Write Only)
bits : 9 - 9 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PDMA Software Request Register
address_offset : 0x408 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWREQ0 : PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ1 : PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ2 : PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ3 : PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ4 : PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ5 : PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ6 : PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ7 : PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ8 : PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 8 - 8 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ9 : PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 9 - 9 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
PDMA Channel Request Status Register
address_offset : 0x40C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REQSTS0 : PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS1 : PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS2 : PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS3 : PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS4 : PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS5 : PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS6 : PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS7 : PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS8 : PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS9 : PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
PDMA Fixed Priority Setting Register
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPRISET0 : PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET1 : PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET2 : PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET3 : PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET4 : PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET5 : PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET6 : PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET7 : PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET8 : PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET9 : PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
End of enumeration elements list.
PDMA Fixed Priority Clear Register
address_offset : 0x414 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FPRICLR0 : PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR1 : PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR2 : PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR3 : PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR4 : PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR5 : PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR6 : PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR7 : PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR8 : PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 8 - 8 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR9 : PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 9 - 9 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
PDMA Interrupt Enable Register
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN0 : PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN1 : PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN2 : PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN3 : PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN4 : PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN5 : PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN6 : PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN7 : PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN8 : PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN9 : PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
PDMA Interrupt Status Register
address_offset : 0x41C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABTIF : PDMA Read/Write Target Abort Interrupt Flag (Read Only)
This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No AHB bus ERROR response received
#1 : 1
AHB bus ERROR response received
End of enumeration elements list.
TDIF : Transfer Done Interrupt Flag (Read Only)
This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not finished yet
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TEIF : Table Empty Interrupt Flag (Read Only)
This bit indicates PDMA channel scatter-gather table is empty. User can read PDMA_SCATSTS register to indicate which channel scatter-gather table is empty.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel scatter-gather table is not empty
#1 : 1
PDMA channel scatter-gather table is empty
End of enumeration elements list.
REQTOF0 : PDMA Channel n Request Time-out Flag
This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No request time-out
#1 : 1
Peripheral request time-out
End of enumeration elements list.
REQTOF1 : PDMA Channel n Request Time-out Flag
This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No request time-out
#1 : 1
Peripheral request time-out
End of enumeration elements list.
PDMA Channel Read/Write Target Abort Flag Register
address_offset : 0x420 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABTIF0 : PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF1 : PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF2 : PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF3 : PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF4 : PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF5 : PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF6 : PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF7 : PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF8 : PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF9 : PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
PDMA Channel Transfer Done Flag Register
address_offset : 0x424 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDIF0 : PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF1 : PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF2 : PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF3 : PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF4 : PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF5 : PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF6 : PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF7 : PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF8 : PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF9 : PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
PDMA Scatter-gather Table Empty Status Register
address_offset : 0x428 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEMPTYF0 : Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel scatter-gather table is not empty
#1 : 1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
End of enumeration elements list.
TEMPTYF1 : Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel scatter-gather table is not empty
#1 : 1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
End of enumeration elements list.
TEMPTYF2 : Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel scatter-gather table is not empty
#1 : 1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
End of enumeration elements list.
TEMPTYF3 : Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel scatter-gather table is not empty
#1 : 1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
End of enumeration elements list.
TEMPTYF4 : Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel scatter-gather table is not empty
#1 : 1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
End of enumeration elements list.
TEMPTYF5 : Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel scatter-gather table is not empty
#1 : 1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
End of enumeration elements list.
TEMPTYF6 : Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel scatter-gather table is not empty
#1 : 1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
End of enumeration elements list.
TEMPTYF7 : Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel scatter-gather table is not empty
#1 : 1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
End of enumeration elements list.
TEMPTYF8 : Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel scatter-gather table is not empty
#1 : 1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
End of enumeration elements list.
TEMPTYF9 : Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel scatter-gather table is not empty
#1 : 1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
End of enumeration elements list.
PDMA Transfer Active Flag Register
address_offset : 0x42C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXACTF0 : PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF1 : PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF2 : PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF3 : PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF4 : PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF5 : PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF6 : PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF7 : PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF8 : PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF9 : PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
PDMA Time-out Prescaler Register
address_offset : 0x430 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTPSC0 : PDMA Channel 0 Time-out Clock Source Prescaler Bits
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
PDMA channel 0 time-out clock source is HCLK/28
#001 : 1
PDMA channel 0 time-out clock source is HCLK/29
#010 : 2
PDMA channel 0 time-out clock source is HCLK/210
#011 : 3
PDMA channel 0 time-out clock source is HCLK/211
#100 : 4
PDMA channel 0 time-out clock source is HCLK/212
#101 : 5
PDMA channel 0 time-out clock source is HCLK/213
#110 : 6
PDMA channel 0 time-out clock source is HCLK/214
#111 : 7
PDMA channel 0 time-out clock source is HCLK/215
End of enumeration elements list.
TOUTPSC1 : PDMA Channel 1 Time-out Clock Source Prescaler Bits
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
PDMA channel 1 time-out clock source is HCLK/28
#001 : 1
PDMA channel 1 time-out clock source is HCLK/29
#010 : 2
PDMA channel 1 time-out clock source is HCLK/210
#011 : 3
PDMA channel 1 time-out clock source is HCLK/211
#100 : 4
PDMA channel 1 time-out clock source is HCLK/212
#101 : 5
PDMA channel 1 time-out clock source is HCLK/213
#110 : 6
PDMA channel 1 time-out clock source is HCLK/214
#111 : 7
PDMA channel 1 time-out clock source is HCLK/215
End of enumeration elements list.
PDMA Time-out Enable Register
address_offset : 0x434 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTEN0 : PDMA Channel n Time-out Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel n time-out function Disabled
#1 : 1
PDMA Channel n time-out function Enabled
End of enumeration elements list.
TOUTEN1 : PDMA Channel n Time-out Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel n time-out function Disabled
#1 : 1
PDMA Channel n time-out function Enabled
End of enumeration elements list.
PDMA Time-out Interrupt Enable Register
address_offset : 0x438 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTIEN0 : PDMA Channel n Time-out Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel n time-out interrupt Disabled
#1 : 1
PDMA Channel n time-out interrupt Enabled
End of enumeration elements list.
TOUTIEN1 : PDMA Channel n Time-out Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel n time-out interrupt Disabled
#1 : 1
PDMA Channel n time-out interrupt Enabled
End of enumeration elements list.
PDMA Scatter-gather Descriptor Table Base Address Register
address_offset : 0x43C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCATBA : PDMA Scatter-gather Descriptor Table Address Register
In Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is
Note: Only useful in Scatter-Gather mode.
bits : 16 - 31 (16 bit)
access : read-write
Source Address Register of PDMA Channel n
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Channel 0 and Channel 1 Time-out Counter Register
address_offset : 0x440 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC0 : Time-out Counter for Channel 0
This controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock.
bits : 0 - 15 (16 bit)
access : read-write
TOC1 : Time-out Counter for Channel 1
This controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock. The example of time-out period can refer TOC0 bit description.
bits : 16 - 31 (16 bit)
access : read-write
PDMA Channel Reset Control Register
address_offset : 0x460 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESET0 : PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n
End of enumeration elements list.
RESET1 : PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n
End of enumeration elements list.
RESET2 : PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n
End of enumeration elements list.
RESET3 : PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n
End of enumeration elements list.
RESET4 : PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n
End of enumeration elements list.
RESET5 : PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n
End of enumeration elements list.
RESET6 : PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n
End of enumeration elements list.
RESET7 : PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n
End of enumeration elements list.
RESET8 : PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n
End of enumeration elements list.
RESET9 : PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n
End of enumeration elements list.
Destination Address Register of PDMA Channel n
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Channel 0 to Channel 3 Request Source Select Register
address_offset : 0x480 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQSRC0 : Channel 0 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.
Note 1: A request source can't assign to two channels at the same time.
Note 2: This field is useless when transfer between memory and memory.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Disable PDMA
1 : 1
Reserved.
4 : 4
Channel connects to UART0_TX
5 : 5
Channel connects to UART0_RX
6 : 6
Channel connects to UART1_TX
7 : 7
Channel connects to UART1_RX
8 : 8
Channel connects to UART2_TX
9 : 9
Channel connects to UART2_RX
10 : 10
Reserved
11 : 11
Reserved
12 : 12
Reserved
13 : 13
Reserved
14 : 14
Reserved
15 : 15
Reserved
16 : 16
Channel connects to SPI0_TX
17 : 17
Channel connects to SPI0_RX
18 : 18
Channel connects to SPI1_TX
19 : 19
Channel connects to SPI1_RX
20 : 20
Channel connects to ADC_RX
21 : 21
Reserved
22 : 22
Reserved
23 : 23
Reserved
24 : 24
Reserved
25 : 25
Reserved
26 : 26
Reserved
27 : 27
Reserved.
28 : 28
Channel connects to I2C0_TX
29 : 29
Channel connects to I2C0_RX
30 : 30
Channel connects to I2C1_TX
31 : 31
Channel connects to I2C1_RX
32 : 32
Channel connects to TMR0
33 : 33
Channel connects to TMR1
34 : 34
Channel connects to TMR2
35 : 35
Channel connects to TMR3
36 : 36
Channel connects to LLSI0
37 : 37
Channel connects to LLSI1
38 : 38
Channel connects to LLSI2
39 : 39
Channel connects to LLSI3
40 : 40
Channel connects to LLSI4
41 : 41
Channel connects to LLSI5
42 : 42
Channel connects to LLSI6
43 : 43
Channel connects to LLSI7
44 : 44
Channel connects to LLSI8
45 : 45
Channel connects to LLSI9
End of enumeration elements list.
REQSRC1 : Channel 1 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 13 (6 bit)
access : read-write
REQSRC2 : Channel 2 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 21 (6 bit)
access : read-write
REQSRC3 : Channel 3 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 29 (6 bit)
access : read-write
PDMA Channel 4 to Channel 7 Request Source Select Register
address_offset : 0x484 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQSRC4 : Channel 4 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 5 (6 bit)
access : read-write
REQSRC5 : Channel 5 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 13 (6 bit)
access : read-write
REQSRC6 : Channel 6 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 21 (6 bit)
access : read-write
REQSRC7 : Channel 7 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 29 (6 bit)
access : read-write
PDMA Channel 8 to Channel 9 Request Source Select Register
address_offset : 0x488 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQSRC8 : Channel 8 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 8. User can configure the peripheral setting by REQSRC8.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 5 (6 bit)
access : read-write
REQSRC9 : Channel 9 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 9. User can configure the peripheral setting by REQSRC9.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 13 (6 bit)
access : read-write
First Scatter-gather Descriptor Table Offset of PDMA Channel n
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset of PDMA Channel n
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset of PDMA Channel n
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset of PDMA Channel n
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : PDMA Transfer Destination Address Register
This field indicates a 32-bit destination address of PDMA controller.
bits : 0 - 31 (32 bit)
access : read-write
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset of PDMA Channel n
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset of PDMA Channel n
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURADDR : PDMA Current Description Address Register (Read Only)
This field indicates a 32-bit current external description address of PDMA controller.
Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
bits : 0 - 31 (32 bit)
access : read-only
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset of PDMA Channel n
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIRST : PDMA First Descriptor Table Offset
This field indicates the offset of the first descriptor table address in system memory.
Write Operation:
If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the first descriptor table is started from 0x2000_0100, then this field must be filled with 0x0100.
Read Operation:
When operating in scatter-gather mode, the last two bits FIRST[1:0] will become reserved.
Note 1: The first descriptor table address must be word boundary.
Note 2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
bits : 0 - 15 (16 bit)
access : read-write
NEXT : PDMA Next Descriptor Table Offset
This field indicates the offset of next descriptor table address in system memory.
Note: write operation is useless in this field.
bits : 16 - 31 (16 bit)
access : read-write
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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