TIMER0_CTL

TIMER0_CAP

TIMER0_EXTCTL

TIMER0_EINTSTS

TIMER1_CTL

TIMER1_CMP

TIMER1_INTSTS

TIMER1_CNT

TIMER1_CAP

TIMER1_EXTCTL

TIMER1_EINTSTS

TIMER0_CMP

TIMER0_INTSTS

TIMER0_CNT

PSC : Prescale Counter Note: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
bits : 0 - 7 (8 bit)
access : read-write

TRGPDMA : Trigger PDMA Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGBPWM23 : Trigger BPWM23 Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM23.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTRGEN : Inter-timer Trigger Mode Enable Bit Setting this bit will enable the inter-timer trigger capture function. The Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function. Note: For Timer1/3, this bit is ignored and the read back value is always 0.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPSRC : Capture Pin Source Selection
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGSSEL : Trigger Source Select Bit This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGBPWM01 : Trigger BPWM01 Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM01.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGADC : Trigger ADC Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TGLPINSEL : Toggle-output Pin Select
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : Wake-up Function Enable Bit If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EXTCNTEN : Event Counter Mode Enable Bit This bit is for external counting pin function enabled. Note 2: When Timer/Timer INTRGEN is set to 1, this bit is forced to 1. When INTRGEN is 1 and Timer1/Timer3 CAPIF (TIMERx_EINTSTS[0]) is 1, this bit is forced to 0.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTSTS : Timer Active Status Bit (Read Only) This bit indicates the 24-bit up counter status. Note: This bit may active when CNT 0 transition to CNT 1.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RSTCNT : Timer Counter Reset Bit Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1. Note: This bit will be auto cleared.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE : Timer Counting Mode Select
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : Timer Interrupt Enable Bit Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN : Timer Counting Enable Bit Note 3: Setting this bit enable/disable needs 2 * TMR_CLK period to become active. User can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ICEDEBUG : ICE Debug Mode Acknowledge Disable Bit (Write Protect) TIMER counter will keep going no matter CPU is held by ICE or not. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPDAT : Timer Capture Data Register When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
bits : 0 - 23 (24 bit)
access : read-only

CNTPHASE : Timer External Count Phase
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEDGE : Timer External Capture Pin Edge Detect
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEN : Timer Capture Enable Bit This bit enables the capture input function. Note: Timer1/3 CAPEN will be forced to 1 when Timer0/2 INTRGEN is enabled.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPFUNCS : Capture Function Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIEN : Timer External Capture Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPDBEN : Timer External Capture Pin De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx_EXT pin output is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTDBEN : Timer Counter Pin De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF : Timer Capture Interrupt Flag This bit indicates the timer capture interrupt flag status. Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDAT : Timer Comparator Value CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1. Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
bits : 0 - 23 (24 bit)
access : read-write

TIF : Timer Interrupt Flag This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value. Note: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TWKF : Timer Wake-up Flag This bit indicates the interrupt wake-up flag status of timer. Note: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNT : Timer Data Register Read this register to get CNT value. For example: If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value. If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
bits : 0 - 23 (24 bit)
access : read-only