\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
WWDT Reload Counter Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RLDCNT : WWDT Reload Counter Register
Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
Note 1: User can only execute the reload WWDT counter value command when current CNTDAT (WWDT_CNT[5:0]) is between 1 and CMPDAT (WWDT_CTL[21:16]). If user writes 0x00005AA5 in WWDT_RLDCNT register when the current CNTDAT is greater than CMPDAT, WWDT reset system event will be generated immediately.
Note 2: Executing WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also.
bits : 0 - 31 (32 bit)
access : write-only
WWDT Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WWDTEN : WWDT Enable Bit
Set this bit to start WWDT counter counting.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
WWDT counter is stopped
#1 : 1
WWDT counter is starting counting
End of enumeration elements list.
INTEN : WWDT Interrupt Enable Bit
If this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
WWDT counter compare match interrupt disabled
#1 : 1
WWDT counter compare match interrupt enabled
End of enumeration elements list.
PSCSEL : WWDT Counter Prescale Period Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Pre-scale is 1 Max time-out period is 1 * 64 * WWDT_CLK
#0001 : 1
Pre-scale is 2 Max time-out period is 2 * 64 * WWDT_CLK
#0010 : 2
Pre-scale is 4 Max time-out period is 4 * 64 * WWDT_CLK
#0011 : 3
Pre-scale is 8 Max time-out period is 8 * 64 * WWDT_CLK
#0100 : 4
Pre-scale is 16 Max time-out period is 16 * 64 * WWDT_CLK
#0101 : 5
Pre-scale is 32 Max time-out period is 32 * 64 * WWDT_CLK
#0110 : 6
Pre-scale is 64 Max time-out period is 64 * 64 * WWDT_CLK
#0111 : 7
Pre-scale is 128 Max time-out period is 128 * 64 * WWDT_CLK
#1000 : 8
Pre-scale is 192 Max time-out period is 192 * 64 * WWDT_CLK
#1001 : 9
Pre-scale is 256 Max time-out period is 256 * 64 * WWDT_CLK
#1010 : 10
Pre-scale is 384 Max time-out period is 384 * 64 * WWDT_CLK
#1011 : 11
Pre-scale is 512 Max time-out period is 512 * 64 * WWDT_CLK
#1100 : 12
Pre-scale is 768 Max time-out period is 768 * 64 * WWDT_CLK
#1101 : 13
Pre-scale is 1024 Max time-out period is 1024 * 64 * WWDT_CLK
#1110 : 14
Pre-scale is 1536 Max time-out period is 1536 * 64 * WWDT_CLK
#1111 : 15
Pre-scale is 2048 Max time-out period is 2048 * 64 * WWDT_CLK
End of enumeration elements list.
CMPDAT : WWDT Window Compare Value
Set this field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated.
Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current CNTDAT (WWDT_CNT[5:0]) is between 1 and CMPDAT. If user writes 0x00005AA5 in WWDT_RLDCNT register when the current CNTDAT is greater than CMPDAT, WWDT reset system event will be generated immediately.
bits : 16 - 21 (6 bit)
access : read-write
ICEDEBUG : ICE Debug Mode Acknowledge Disable Bit
The WWDT down counter will keep counting no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects WWDT counter counting
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
WWDT Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WWDTIF : WWDT Compare Match Interrupt Flag
This bit indicates that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16]).
Note: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
WWDT CNTDAT matches the CMPDAT
End of enumeration elements list.
WWDTRF : WWDT Timer-out Reset System Flag
If this bit is set to 1, it indicates that system has been reset by WWDT counter time-out reset system event.
Note: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
WWDT time-out reset system event did not occur
#1 : 1
WWDT time-out reset system event occurred
End of enumeration elements list.
WWDT Counter Value Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNTDAT : WWDT Counter Value
CNTDAT will be updated continuously.
bits : 0 - 5 (6 bit)
access : read-only
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