\n
address_offset : 0x0 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x3C Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection :
I2C Control Register 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AA : Assert Acknowledge Control
bits : 2 - 2 (1 bit)
access : read-write
SI : I2C Interrupt Flag
When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
bits : 3 - 3 (1 bit)
access : read-write
STO : I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
bits : 4 - 4 (1 bit)
access : read-write
STA : I2C START Control
Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or Repeat START condition to bus when the bus is free.
bits : 5 - 5 (1 bit)
access : read-write
I2CEN : I2C Controller Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C controller Disabled
#1 : 1
I2C controller Enabled
End of enumeration elements list.
INTEN : Enable Interrupt
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C interrupt Disabled
#1 : 1
I2C interrupt Enabled
End of enumeration elements list.
I2C Clock Divided Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : I2C Clock Divided
Note: The minimum value of I2C_CLKDIV is 4.
bits : 0 - 9 (10 bit)
access : read-write
NFCNT : Noise Filter Count
The register bits control the input filter width.
Note: Filter width Min :3*PCLK, Max : 18*PCLK
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : 0
Filter width 3*PCLK
1 : 1
Filter width 4*PCLK
End of enumeration elements list.
I2C Time-out Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOIF : Time-out Flag
This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
Note: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
TOCDIV4 : Time-out Counter Input Clock Divided by 4
When enabled, the time-out period is extended 4 times.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out period is extend 4 times Disabled
#1 : 1
Time-out period is extend 4 times Enabled
End of enumeration elements list.
TOCEN : Time-out Counter Enable Bit
When enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out counter Disabled
#1 : 1
Time-out counter Enabled
End of enumeration elements list.
I2C Slave Address Register1
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Slave Address Register2
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Slave Address Register3
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Slave Address Mask Register0
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMSK : I2C Address Mask
I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function cannot use address mask.
bits : 1 - 10 (10 bit)
access : read-write
Enumeration:
0 : 0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
1 : 1
Mask Enabled (the received corresponding address bit is don't care.)
End of enumeration elements list.
I2C Slave Address Mask Register1
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Slave Address Mask Register2
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Slave Address Mask Register3
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Wake-up Control Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKEN : I2C Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C wake-up function Disabled
#1 : 1
I2C wake-up function Enabled
End of enumeration elements list.
NHDBUSEN : I2C No Hold BUS Enable Bit
Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C hold bus after wake-up
#1 : 1
I2C don't hold bus after wake-up
End of enumeration elements list.
I2C Slave Address Register0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GC : General Call Function
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
General Call Function Disabled
#1 : 1
General Call Function Enabled
End of enumeration elements list.
ADDR : I2C Address
The content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
Note: When software sets 10'h000, the address cannot be used.
bits : 1 - 10 (10 bit)
access : read-write
I2C Wake-up Status Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKIF : I2C Wake-up Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
WKAKDONE : Wakeup Address Frame Acknowledge Bit Done
Note: This bit can't release WKIF. Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The ACK bit cycle of address match frame isn't done
#1 : 1
The ACK bit cycle of address match frame is done in power-down
End of enumeration elements list.
WRSTSWK : Read/Write Status Bit in Address Wakeup Frame (Read Only)
Note: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Write command be record on the address match wakeup frame
#1 : 1
Read command be record on the address match wakeup frame
End of enumeration elements list.
I2C Control Register 1
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPDMAEN : PDMA Transmit Channel Available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit PDMA function Disabled
#1 : 1
Transmit PDMA function Enabled
End of enumeration elements list.
RXPDMAEN : PDMA Receive Channel Available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive PDMA function Disabled
#1 : 1
Receive PDMA function Enabled
End of enumeration elements list.
PDMARST : PDMA Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the I2C request to PDMA
End of enumeration elements list.
PDMASTR : PDMA Stretch Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C send STOP automatically after PDMA transfer done. (only master TX)
#1 : 1
I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX)
End of enumeration elements list.
ADDR10EN : Address 10-bit Function Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Address match 10-bit function Disabled
#1 : 1
Address match 10-bit function Enabled
End of enumeration elements list.
I2C Status Register 1
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADMAT0 : I2C Address 0 Match Status
When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
ADMAT1 : I2C Address 1 Match Status
When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
ADMAT2 : I2C Address 2 Match Status
When address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write
ADMAT3 : I2C Address 3 Match Status
When address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write
ONBUSY : On Bus Busy (Read Only)
Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
The bus is IDLE (both SCL and SDA High)
#1 : 1
The bus is busy
End of enumeration elements list.
I2C Timing Configure Control Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STCTL : Setup Time Configure Control
This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
Note: Setup time setting should not make SCL output less than three PCLKs.
bits : 0 - 8 (9 bit)
access : read-write
HTCTL : Hold Time Configure Control
This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
bits : 16 - 24 (9 bit)
access : read-write
I2C Bus Management Control Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACKMEN : Acknowledge Control by Manual
In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave byte control Disabled
#1 : 1
Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCL signal low between the 8th and 9th SCL pulse
End of enumeration elements list.
PECEN : Packet Error Checking Calculation Enable Bit
Note: When I2C enters Power-down mode, the bit should be enabled after wake-up if needed PEC calculation.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Packet Error Checking Calculation Disabled
#1 : 1
Packet Error Checking Calculation Enabled
End of enumeration elements list.
BMDEN : Bus Management Device Default Address Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Device default address Disable. When the address 0'b1100001x comes and either BMDEN or ACKMEN is disabled, the device responses NACK
#1 : 1
Device default address Enabled. When the address 0'b1100001x comes and both BMDEN and ACKMEN are enabled, the device responses ACK
End of enumeration elements list.
BMHEN : Bus Management Host Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Host function Disabled
#1 : 1
Host function Enabled
End of enumeration elements list.
ALERTEN : Bus Management Alert Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
BM_ALERT pin not supported
#1 : 1
Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
BM_ALERT pin supported
End of enumeration elements list.
SCTLOSTS : Suspend/Control Data Output Status
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The output of SUSCON pin is low
#1 : 1
The output of SUSCON pin is high
End of enumeration elements list.
SCTLOEN : Suspend or Control Pin Output Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SUSCON pin in input
#1 : 1
The output enable is active on the SUSCON pin
End of enumeration elements list.
BUSEN : BUS Enable Bit
Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The system management function Disabled
#1 : 1
The system management function Enabled
End of enumeration elements list.
PECTXEN : Packet Error Checking Byte Transmission/Reception
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No PEC transfer
#1 : 1
PEC transmission is requested
End of enumeration elements list.
BUSTOCHK : Timer Check in Idle State
The BUSTOCHK is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.
Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
BUSTOCHK is used to calculate the clock low period in bus active
#1 : 1
BUSTOCHK is used to calculate the IDLE period in bus Idle
End of enumeration elements list.
PECCLR : PEC Clear at Repeat
The calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit used to enable the condition of Repeat START can clear the PEC calculation.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PEC calculation is cleared by 'Repeat START' function Disabled
#1 : 1
PEC calculation is cleared by 'Repeat START' function Enabled
End of enumeration elements list.
ACKM9SI : Acknowledge Manual Enable Extra SI Interrupt
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
#1 : 1
There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
End of enumeration elements list.
BCDIEN : Packet Error Checking Byte Count Done Interrupt Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Byte count done interrupt Disabled
#1 : 1
Byte count done interrupt Enabled
End of enumeration elements list.
PECDIEN : Packet Error Checking Byte Transfer Done Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PEC transfer done interrupt Disabled
#1 : 1
PEC transfer done interrupt Enabled
End of enumeration elements list.
I2C Bus Management Timer Control Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSTOEN : Bus Time Out Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock low time-out detection Disabled
#1 : 1
Bus clock low time-out detection Enabled (bus clock is low for more than BUSTO (I2C_BUSTOUT[7:0]) (in BIDLE=0) or high more than BUSTO (in BIDLE =1)
End of enumeration elements list.
CLKTOEN : Cumulative Clock Low Time Out Enable Bit
For Master, it calculates the period from START to ACK.
For Slave, it calculates the period from START to STOP.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Cumulative clock low time-out detection Disabled
#1 : 1
Cumulative clock low time-out detection Enabled
End of enumeration elements list.
BUSTOIEN : Time-out Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SCL low time-out interrupt Disabled.
Bus IDLE time-out interrupt Disabled
#1 : 1
SCL low time-out interrupt Enabled.
Bus IDLE time-out interrupt Enabled
End of enumeration elements list.
CLKTOIEN : Extended Clock Time Out Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock time out interrupt Disabled
#1 : 1
Clock time out interrupt Enabled
End of enumeration elements list.
TORSTEN : Time Out Reset Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C state machine reset Disabled
#1 : 1
I2C state machine reset Enabled. (The clock and data bus will be released to high.)
End of enumeration elements list.
I2C Bus Management Status Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSY : Bus Busy (Read Only)
Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Bus is IDLE (both SCL and SDA High)
#1 : 1
Bus is busy
End of enumeration elements list.
BCDONE : Byte Count Transmission/Receive Done
Note: Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Byte count transmission/ receive is not finished when the PECEN is set
#1 : 1
Byte count transmission/ receive is finished when the PECEN is set
End of enumeration elements list.
PECERR : PEC Error in Reception
Note: Software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PEC value equal the received PEC data packet
#1 : 1
PEC value doesn't match the receive PEC data packet
End of enumeration elements list.
ALERT : SMBus Alert Status
Note: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SMBALERT pin state is low.
No SMBALERT event
#1 : 1
SMBALERT pin state is high.
There is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1
End of enumeration elements list.
SCTLDIN : Bus Suspend or Control Signal Input Status (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
The input status of SUSCON pin is 0
#1 : 1
The input status of SUSCON pin is 1
End of enumeration elements list.
BUSTO : Bus Time-out Status
In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
Note: Software can write 1 to clear this bit.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
There is no any time-out or external clock time-out
#1 : 1
A time-out or external clock time-out occurred
End of enumeration elements list.
CLKTO : Clock Low Cumulate Time-out Status
Note: Software can write 1 to clear this bit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Cumulative clock low is no any time-out
#1 : 1
Cumulative clock low time-out occurred
End of enumeration elements list.
PECDONE : PEC Byte Transmission/Receive Done
Note: Software can write 1 to clear this bit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PEC transmission/ receive is not finished when the PECEN is set
#1 : 1
PEC transmission/ receive is finished when the PECEN is set
End of enumeration elements list.
I2C Packet Error Checking Byte Number Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLDSIZE : Transfer Byte Number
The transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.
Note: The byte number counting includes address, command code, and data frame.
bits : 0 - 8 (9 bit)
access : read-write
I2C Packet Error Checking Byte Value Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PECCRC : Packet Error Checking Byte Value
bits : 0 - 7 (8 bit)
access : read-only
I2C Bus Management Timer Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSTO : Bus Management Time-out Value
Indicates the bus time-out value in bus is IDLE or SCL low.
Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
bits : 0 - 7 (8 bit)
access : read-write
I2C Bus Management Clock Low Timer Register
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKTO : Bus Clock Low Timer
The field is used to configure the cumulative clock extension time-out.
Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and cleared to 0 first in the BUSEN is set.
bits : 0 - 7 (8 bit)
access : read-write
I2C Data Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT : I2C Data
Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
bits : 0 - 7 (8 bit)
access : read-write
I2C Status Register 0
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATUS : I2C Status
bits : 0 - 7 (8 bit)
access : read-only
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