LLSI_CTL

LLSI_DATA

LLSI_PCNT

LLSI_CLKDIV

LLSI_STATUS

LLSI_OCTL

LLSI_RSTPERIOD

LLSI_PERIOD

LLSI_DUTY

LLSIEN : LLSI Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTCEN : Reset Command Function Enable Bit Note: If this bit is enabled, when FIFO and shift register are both empty, LLSI will send reset command out.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UNDFLINTEN : Underflow Interrupt Enable Bit Note: If this bit is enabled, when the UNDFLIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FENDINTEN : Frame End Interrupt Enable Bit Note: If this bit is enabled, when the FENDIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTCINTEN : Reset Command Interrupt Enable Bit Note: If this bit is enabled, when the RSTCIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EMPINTEN : FIFO Empty Interrupt Enable Bit Note: If this bit is enabled, when the EMPIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FULINTEN : FIFO FULL Interrupt Enable Bit Note: If this bit is enabled, when the FULIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTHIEN : Transmit FIFO Threshold Interrupt Enable Bit Note: This bit is only supported in software mode.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LLSIMODE : LLSI Mode Select
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

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OFDEF : Output Format Define
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTH : Transmit FIFO Threshold If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
bits : 16 - 17 (2 bit)
access : read-write

DATA : Data Transmit Register The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers.
bits : 0 - 31 (32 bit)
access : write-only

PCNT : Pixel Count Register User should write a frame size to this register before transfer. For example, if there are a total of 5 LED (5 pixels) in frame, user should write 5 to this control register.
bits : 0 - 11 (12 bit)
access : read-write

DIVIDER : LLSI Clock Divider It indicates the LLSI clock,
bits : 0 - 7 (8 bit)
access : read-write

RSTCIF : Reset Command Interrupt Flag This bit indicates that LLSI has finished reset command transmission.
bits : 0 - 0 (1 bit)
access : read-write

EMPIF : FIFO Empty Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FULIF : FIFO Full Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTHIF : Transmit FIFO Threshold Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UNDFLIF : Under Flow Interrupt Flag Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes. Software can write 1 to clear this bit.
bits : 4 - 4 (1 bit)
access : read-write

FENDIF : Frame End Interrupt Flag This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1. User can use this flag to prepare data in advance. Software can write 1 to clear this bit.
bits : 5 - 5 (1 bit)
access : read-write

LDT : Last Data Transmit
bits : 8 - 8 (1 bit)
access : read-write

IDOS : Idle Output Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTPERIOD : Reset Command Period This field is used to adjust the time of reset command.
bits : 0 - 15 (16 bit)
access : read-write

PERIOD : LLSI Period Register This field is used to define data transfer time (TH+TL).
bits : 0 - 7 (8 bit)
access : read-write

T0H : T0H Data Register This field is used to define the time of T0H.
bits : 0 - 7 (8 bit)
access : read-write

T1H : T1H Data Register This field is used to define the time of T1H.
bits : 16 - 23 (8 bit)
access : read-write