\n
address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection :
D0TCM/D1TCM ECC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ECCMOD : ECC enable [D0TCM, D1TCM]
bits : 0 - 0 (1 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read
KEY_CODE : When TCMDECCCNT.KEY_CODE is set to 0x3CA5 , TCMDECCCNT is updating.
bits : 16 - 47 (32 bit)
access : read-write
D0TCM 1-bit Error Address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SBEADD : The 1-bit error address [D0TCM]
bits : 0 - 31 (32 bit)
access : read
D1TCM 1-bit Error Address Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SBEADD : The 1-bit error address [D1TCM]
bits : 0 - 31 (32 bit)
access : read
D0TCM/D1TCM 1-bit Error Detection Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
D0SBE : 1-bit error detection bit [D0TCM]
bits : 0 - 0 (1 bit)
access : read
__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read
D0MASTER : Memory access at 1-bit error [D0TCM]
bits : 4 - 11 (8 bit)
access : read
D1SBE : 1-bit error detection bit [D1TCM]
bits : 8 - 16 (9 bit)
access : read
__reserve1 : 0 is always read out.
bits : 9 - 20 (12 bit)
access : read
D1MASTER : Memory access at 1-bit error[D1TCM]
bits : 12 - 27 (16 bit)
access : read
D0TCM/D1TCM 1-bit Error Detection Clear Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
D0SBECLR : Clear the 1-bit error detection [D0TCM]
bits : 0 - 0 (1 bit)
access : read-write
D1SBECLR : Clear the 1-bit error detection [D1TCM]
bits : 1 - 2 (2 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 2 - 9 (8 bit)
access : read
D0TCM 2-bit Error Address Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MBEADD : The 2-bit error or hard error address [D0TCM]
bits : 0 - 31 (32 bit)
access : read
D1TCM 2-bit Error Address Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MBEADD : The 2-bit error or hard error address [D1TCM]
bits : 0 - 31 (32 bit)
access : read
D0TCM/D1TCM 2-bit Error Detection Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
D0MBE : 2-bit error detection bit [D0TCM]
bits : 0 - 0 (1 bit)
access : read
D0HDE : Hard error detection bit [D0TCM]
bits : 1 - 2 (2 bit)
access : read
__reserve0 : 0 is always read out.
bits : 2 - 5 (4 bit)
access : read
D0MASTER : Memory access at 2-bit error [D0TCM]
bits : 4 - 11 (8 bit)
access : read
D1MBE : 2-bit error detection bit [D1TCM]
bits : 8 - 16 (9 bit)
access : read
D1HDE : Hard error detection bit [D1TCM]
bits : 9 - 18 (10 bit)
access : read
__reserve1 : 0 is always read out.
bits : 10 - 21 (12 bit)
access : read
D1MASTER : Memory access at 2-bit error[D1TCM]
bits : 12 - 27 (16 bit)
access : read
D0TCM/D1TCM 2-bit Error Detection Clear Register
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
D0MBECLR : Clear the 2-bit error and hard error detection [D0TCM]
bits : 0 - 0 (1 bit)
access : read-write
D1MBECLR : Clear the 2-bit error and hard error detection [D1TCM]
bits : 1 - 2 (2 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 2 - 4 (3 bit)
access : read
__reserve1 : 0 is always read out.
bits : 3 - 10 (8 bit)
access : read
ITCM ECC Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ECCMOD : ECC enable [ITCM]
bits : 0 - 0 (1 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read
KEY_CODE : When TCMIECCCNT.KEY_CODE is set to 0xA5C3 , TCMIECCCNT is updating.
bits : 16 - 47 (32 bit)
access : read-write
ITCM Wait Setting Register
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
WAIT : Wait setting [ITCM]
bits : 0 - 0 (1 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read
ITCM Check Bit Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CBEN : Check bit read/write enable [ITCM]
bits : 0 - 0 (1 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read
KEY_CODE : When TCMICBEN.KEY_CODE is set to 0xA5C3 , TCMICBEN is updating.
bits : 16 - 47 (32 bit)
access : read-write
D0TCM/D1TCM Wait Setting Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
WAIT : Wait setting [D0TCM, D1TCM]
bits : 0 - 0 (1 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read
ITCM 1-bit Error Address Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SBEADD : The 1bit error address [ITCM]
bits : 0 - 31 (32 bit)
access : read
ITCM 1-bit Error Detection Register
address_offset : 0x48 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
SBE : 1-bit error detection bit [ITCM]
bits : 0 - 0 (1 bit)
access : read
__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read
MASTER : Memory access at 1-bit error [ITCM]
bits : 4 - 11 (8 bit)
access : read
ITCM 1-bit Error Detection Clear Register
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
SBECLR : Clear the 1-bit error detection [ITCM]
bits : 0 - 0 (1 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read
ITCM 2-bit Error Address Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MBEADD : The 2-bit error or hard error address [ITCM]
bits : 0 - 31 (32 bit)
access : read
ITCM 2-bit Error Detection Register
address_offset : 0x58 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
MBE : 2-bit error detection bit [ITCM]
bits : 0 - 0 (1 bit)
access : read
HDE : Hard error detection bit [ITCM]
bits : 1 - 2 (2 bit)
access : read
__reserve0 : 0 is always read out.
bits : 2 - 5 (4 bit)
access : read
MASTER : Memory access at 2-bit error [ITCM]
bits : 4 - 11 (8 bit)
access : read
ITCM 2-bit Error Detection Clear Register
address_offset : 0x5C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
MBECLR : Clear the 2-bit error and hard error detection [ITCM]
bits : 0 - 0 (1 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read
D0TCM/D1TCM Check Bit Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
D0CBEN : Check bit read/write enable [D0TCM]
bits : 0 - 0 (1 bit)
access : read-write
D1CBEN : Check bit read/write enable [D1TCM]
bits : 1 - 2 (2 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read
KEY_CODE : When TCMDCBEN.KEY_CODE is set to 0x3CA5 , TCMDCBEN is updating.
bits : 16 - 47 (32 bit)
access : read-write
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